Construction of III-V CMOS Photonics
Project/Area Number |
22686034
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Research Category |
Grant-in-Aid for Young Scientists (A)
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Allocation Type | Single-year Grants |
Research Field |
Electron device/Electronic equipment
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Research Institution | The University of Tokyo |
Principal Investigator |
TAKENAKA Mitsuru 東京大学, 工学(系)研究科(研究院), 准教授 (20451792)
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Project Period (FY) |
2010-04-01 – 2014-03-31
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Project Status |
Completed (Fiscal Year 2013)
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Budget Amount *help |
¥25,740,000 (Direct Cost: ¥19,800,000、Indirect Cost: ¥5,940,000)
Fiscal Year 2013: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
Fiscal Year 2012: ¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2011: ¥7,410,000 (Direct Cost: ¥5,700,000、Indirect Cost: ¥1,710,000)
Fiscal Year 2010: ¥10,920,000 (Direct Cost: ¥8,400,000、Indirect Cost: ¥2,520,000)
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Keywords | 光電子集積回路 / CMOSフォトニクス / 細線導波路 / 光変調器 / 受光器 / InGaAs MOSFET / 基板貼り合せ / III-V-OI基板 / 光集積回路 / 光スイッチ / 化合物半導体 / MOSトランジスタ / 基板貼り合わせ / CMOS photonics / III-V MOSFET |
Research Abstract |
We have successfully established the fabrication procedure of III-V-on-Insulator (III-V-OI) wafers by using the direct wafer bonding technology. As a result, we have demonstrated high-performance optical switches/modulators and waveguide photodetectors on the III-V-OI wafer in addiction to InP-based photonic-wire passive devices. We have also established the fabrication procedure of InGaAs MOS transistors on the III-V-OI wafer. Thus, we have successfully demonstrated the basic concept of the III-V CMOS photonics platform on which ultra-small III-V-based photonic-wire devices and high-performance III-V-based CMOS transistors can be co-integrated by using the III-V-OI wafer.
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Report
(5 results)
Research Products
(69 results)
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[Journal Article] Impact of Fermi level pinning due to interface traps inside conduction band on the inversion-layer mobility in InxG_a_<1-x> As metal-oxide-semiconductor field effect transistors2013
Author(s)
N. Taoka, M. Yokoyama, S. -H. Kim, R. Suzuki, S. Lee, R. Iida, T. Hoshii, W. Jevasuwan, T. Maeda, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi
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Journal Title
IEEE Transactions on device and materials reliability
Volume: 13
Issue: 4
Pages: 456-462
DOI
Related Report
Peer Reviewed
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[Journal Article] Impact of Fermi level pinning inside conduction band on electron mobility in InGaAs metal-oxide-semiconductor field-effect transistors2013
Author(s)
N. Taoka, M. Yokoyama, S. -H. Kim, R. Suzuki, S. Lee, R. Iida, T. Hoshii, W. Jevasuwan, T. Maeda, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi
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Journal Title
Applied Physics Letters
Volume: 103
Issue: 14
Pages: 143509-143509
DOI
Related Report
Peer Reviewed
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[Journal Article] Electron mobility enhancement of extremely thin body In_<0.7>Ga_<0.3>As-on-insulator metal-oxide-semiconductor field-effect transistors on Si substrates by metal-oxide-semiconductor interface buffer layers2012
Author(s)
S. H. Kim, M. Yokoyama, N. Taoka, R. Iida, S. Lee, R. Nakane, Y. Urabe, N. Miyata, T. Yasuda, H. Yamada, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi
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Journal Title
Appl. Phys. Express
Volume: Vol.5
Issue: 1
Pages: 14201-14201
DOI
NAID
Related Report
Peer Reviewed
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[Journal Article] High performance extremely thin body InGaAs-on-insulator metal-oxide semiconductor field-effect transistors on Si substrates with Ni-InGaAs metal source/drain2011
Author(s)
S. H. Kim, M. Yokoyama, N. Taoka, R. Iida, S. Lee, R. Nakane, Y. Urabe, N. Miyata, T. Yasuda, H. Yamada, N. Fukuhara, M. Hata, M. Takenaka, and S. Takagi
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Journal Title
Appl. Phys. Express
Volume: Vol.4
Issue: 11
Pages: 114201-114201
DOI
NAID
Related Report
Peer Reviewed
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[Presentation] Sub-60 nm deeply-scaled channel length extremely-thin body InxGa1-xAs-on-insulator MOSFETs on a Si with Ni-InGaAs metal S/D and MOS interface buffer Engineering2012
Author(s)
S. H. Kim, M. Yokoyama, N. Taoka, R. Nakane, T. Yasuda, O. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, S. Takagi
Organizer
VLSI Symposium
Place of Presentation
Honolulu, United Sates of America
Related Report
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[Presentation] Enhancement technologies and physical understanding of electron mobility in III-V n-MOSFETs with strain and MOS interface buffer engineering2011
Author(s)
S.H. Kim, M. Yokoyama, N. Taoka, R. Nakane, T. Yasuda, M. Ichikawa, N. Fukuhara, M. Hata, M. Takenaka, S. Takagi
Organizer
International Electron Devices Meeting
Place of Presentation
Washington D.C., United States of America
Related Report
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[Presentation] High performance extremely-thin body III-V-on-insulator MOSFETs on a Si substrate with Ni-InGaAs metal S/D and MOS interface buffer engineering2011
Author(s)
S.H. Kim, M. Yokoyama, N. Taoka, R. Iida, S. Lee, R. Nakane, Y. Urabe, N. Miyata, T. Yasuda, H. Yamada, N. Fukuhara, M. Hata, M. Takenaka and S. Takagi
Organizer
VLSI Symposium
Place of Presentation
Rihga Royal Hotel Kyoto, Kyoto
Related Report
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[Presentation] Ultra-small, low-crosstalk, electrically-driven InGaAsP photonic-wire optical switches on III-V CMOS photonics platform
Author(s)
Y. Ikku, M.Yokoyama, O. Ichikawa, T. Osada, M. Hata, M. Takenaka, and S. Takagi
Organizer
Optical Fiber Communication Conference
Place of Presentation
Moscone center, San Francisco, USA
Related Report
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