Scalable RF CMOS chip for tera-bit wireless communications
Project/Area Number |
22686037
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Research Category |
Grant-in-Aid for Young Scientists (A)
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Allocation Type | Single-year Grants |
Research Field |
Communication/Network engineering
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Research Institution | Tokyo Institute of Technology |
Principal Investigator |
OKADA Kenichi 東京工業大学, 大学院・理工学研究科, 准教授 (70361772)
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Project Period (FY) |
2010 – 2012
|
Project Status |
Completed (Fiscal Year 2012)
|
Budget Amount *help |
¥19,500,000 (Direct Cost: ¥15,000,000、Indirect Cost: ¥4,500,000)
Fiscal Year 2012: ¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000)
Fiscal Year 2011: ¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000)
Fiscal Year 2010: ¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000)
|
Keywords | 電子回路網 / ミリ波 / CMOS / 無線通信 / 高周波回路 / スケーラブル / Digital RF / RF / シリコン / テラヘルツ |
Research Abstract |
In this work, a fundamental theory of scalable RF transceiver has been studies for realizing 1Tbps ultra-high-speed wireless communication. The key technology for the scalable RF transceiver is the improvement of gain, linearity and noise characteristics, and a circuit technique to maintain the circuit performance even with the process fluctuation. In this work, the proposed digital RF technique is applied to realize a self-calibration of the60GHz wireless transceiver implemented by 65nm CMOS. The phase noise degradation is avoided by using the proposed injection-locked oscillator, which results in a 20-dB improvement in the phase noise. Finally, a 20Gbps wireless transceiver has been realized, which is the fastest among wireless transceiver ICs.
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Report
(4 results)
Research Products
(221 results)
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[Journal Article] A 24dB Gain 51-68GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors2012
Author(s)
Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Yoichi Kawano, Tatsuya Hirose, Kenichi Okada, and Akira Matsuzawa
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Journal Title
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume: Vol.E95-A,No.2
Pages: 498-505
NAID
Related Report
Peer Reviewed
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[Presentation] A Digitally-Calibrated20-Gb/s 60-GHz Direct-Conversion Transceiver in 65-nm CMOS2013
Author(s)
Seitaro Kawai, Ryo Minami, Yuki Tsukui, Yasuaki Takeuchi, Hiroki Asada, Ahmed Musa, Rui Murakami, Takahiro Sato, Qinghong Bu, Ning Li, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa
Organizer
IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Place of Presentation
Seattle, WA
Year and Date
2013-06-03
Related Report
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[Presentation] A 60GHz 16Gb/s 16QAM Low-Power Direct-Conversion Transceiver Using Capacitive Cross-Coupling Neutralization in 65nm CMOS2011
Author(s)
Hiroki Asada, Keigo Bunsen, Kota Matsushita, Rui Murakami, Qinghong Bu, Ahmed Musa, Takahiro Sato, Tatsuya Yamaguchi, Ryo Minami, Toshihiko Ito, Kenichi Okada, and Akira Matsuzawa
Organizer
IEEE Asian Solid-State Circuits Conference (A-SSCC)
Place of Presentation
Jeju, Korea
Year and Date
2011-11-16
Related Report
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[Presentation] A 60-GHz16QAM/8PSK/QPSK/BPSKDirect-Conversion Transceiver for IEEE802.15.3c2011
Author(s)
Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, and Akira Matsuzawa
Organizer
IEEE International Solid-State Circuits Conference (ISSCC)
Place of Presentation
San Francisco, CA
Year and Date
2011-02-22
Related Report
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[Presentation] 10MHz to 7GHz Quadrature Signal Generation Using a Divide-by-4/3, -3/2, -5/3, -2, -5/2,-3, -4, and -5 Injection-Locked Frequency Divider2010
Author(s)
Shoichi Hara, Kenichi Okada, and Akira Matsuzawa
Organizer
IEEE Symposium on VLSI Circuits (VLSI Circuits)
Place of Presentation
Honolulu, HI
Year and Date
2010-06-16
Related Report
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