A Systematic Test Generation Approach to Achieving VariousTest Qualities for LSIs Based on Mathematical Programming

• Project/Area Number: 22700049
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: Hiroshima City University (2012); Japan Advanced Institute of Science and Technology (2010-2011)
• Principal Investigator: IWAGAKI Tsuyoshi 広島市立大学, 情報科学研究科, 助教 (00397845)
• Project Period (FY): 2010 – 2012
• Project Status: Completed (Fiscal Year 2012)
• Budget Amount: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000); Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000); Fiscal Year 2011: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000); Fiscal Year 2010: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
• Keywords: テスト生成 / 整数計画法 / 充足可能性問題 / 非同期インターコネクト / クロックスキュー / ホールドタイム違反 / 電力制約下テスト / テスト数最小化 / ホールドタイム故障 / 整数計画問題 / テストパターン数最小化 / 検出故障数最大化 / ホールド違反 / 消費電力 / 解の再利用 / インスタンスの類似度 / 変数割当て順序 / 集積回路 / テストスケジューリング / ホールド違反検出 / スキャンチェーン順序

Research Abstract

This work focused attention on mathematical programming (especially, integer programming) as a test generation framework that can flexibly generate various types of tests required for large-scale integrated circuits (LSIs). Several methods have been devised to formulate integer programming models for different test generation problems and to heuristically solve them. This framework allows us to solve these problems with a powerful off-the-shelf solver for integer programming, without developing any newtechniques dedicated to them. The results can lead to enhancing the reliability of LSIs at low cost.

Research Products

• [Journal Article] Flexible test scheduling for an asynchronous on-chip interconnect through special data transfer (2011)
  • Author(s): Tsuyoshi Iwagaki, Eiri Takeda and Mineo Kaneko
  • Journal Title: IEICE Trans. on Fundamentals Volume: E94-A Pages: 2563-2570
  • NAID: 10030533654
  • Peer Reviewed
• [Journal Article] Fiexible test scheduling for an asynchronous on-chip interconnect through special data transfer (2011)
  • Author(s): Tsuyoshi Iwagaki
  • Journal Title: IEICE Trans.on Fundamentals Volume: E94-A Pages: 2563-2570
  • Peer Reviewed
• [Presentation] 解の再利用によるテスト生成のためのハードウェアSATソルバの実装 (2013)
  • Author(s): 向井俊矢, 上田健司, 岩垣剛, 市原英行, 井上智生
  • Organizer: 信学技法
  • Place of Presentation: 東京
  • Year and Date: 2013-02-01
• [Presentation] 解の再利用を用いたSATに基づくテスト生成におけるインスタンス順序と変数割当順序の決定法 (2012)
  • Author(s): 上田健司, 岩垣剛, 市原英行, 井上智生
  • Organizer: 信学技法
  • Place of Presentation: 福岡
  • Year and Date: 2012-11-01
• [Presentation] Exact and heuristic methods of generating compact tests for hold-time violations (2012)
  • Author(s): Tsuyoshi Iwagaki, HideyukiIchihara, Tomoo Inoue and Kewal K. Saluja
  • Organizer: Digest of Papers 13th IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: Niigata
  • Year and Date: 2012-11-01
• [Presentation] A technique for SAT-based test generation through history of reusing solutions (2012)
  • Author(s): Kenji Ueda
  • Organizer: 17th Workshop on Synthesis and System Integration of Mixed Information Technologies
  • Place of Presentation: ビーコンプラザ(大分)
  • Year and Date: 2012-03-08
• [Presentation] A technique for SAT-based testgeneration through history of reusing solutions (2012)
  • Author(s): Kenji Ueda, Fumiyuki Hafuri, Toshiya Mukai, Tsuyoshi Iwagaki, Hideyuki Ichihara and Tomoo Inoue
  • Organizer: Proc. 17th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI '12)
  • Place of Presentation: Oita
  • Year and Date: 2012-03-01
• [Presentation] Exact and heuristic methods of generating compact tests for hold-time violations (2012)
  • Author(s): Tsuyoshi Iwagaki
  • Organizer: IEEE Workshop on RTL and High Level Testing (WRTLT)
  • Place of Presentation: 新潟
• [Presentation] An approach to hardware SAT solvers for test generation based on instance similarity (2011)
  • Author(s): Tsuyoshi Iwagaki
  • Organizer: 12th IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: MNIT Jaipur, India
  • Year and Date: 2011-11-26
• [Presentation] An approach to hardware SAT solvers for test generation based on instance similarity (2011)
  • Author(s): Tsuyoshi Iwagaki, Fumiyuki Hafuri, Kenji Ueda, Toshiya Mukai, Hideyuki Ichihara and Tomoo Inoue
  • Organizer: Digest of Papers 12th IEEE Workshop on RTL and High Level Testing (WRTLT '11)
  • Place of Presentation: Jaipur (India)
  • Year and Date: 2011-11-01
• [Presentation] Power-constrained test generation for hold-time faults using integer linear programming (2011)
  • Author(s): Tsuyoshi Iwagaki
  • Organizer: 4th IEEE International Workshop on Impact of Low-Power Design on Test and Reliability
  • Place of Presentation: Gloshaugen Campus, Trondheim, Norway
  • Year and Date: 2011-05-27
• [Presentation] Power-constrained test generation for hold-time faults using integer linear programming (2011)
  • Author(s): Tsuyoshi Iwagaki and Kewal K. Saluja
  • Organizer: Proc. 4th IEEE International Workshop on Impact of Low-Power Design on Test and Reliability (LPonTR '11)
  • Place of Presentation: Trondheim (Norway)
  • Year and Date: 2011-05-01
• [Presentation] Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations (2011)
  • Author(s): Tsuyoshi Iwagaki
  • Organizer: 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
  • Place of Presentation: Lindner Congress Hotel, Cottbus, Germany
  • Year and Date: 2011-04-13
• [Presentation] Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations (2011)
  • Author(s): Tsuyoshi Iwagaki and Kewal K. Saluja
  • Organizer: Proc. 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '11)
  • Place of Presentation: Cottbus (Germany)
  • Year and Date: 2011-04-01
• [Presentation] On indirect detection of functional hold-time violations using scan shift operations (2011)
  • Author(s): 岩垣剛
  • Organizer: 第44回機能集積情報システム研究会
  • Place of Presentation: 千葉大学(千葉県)
  • Year and Date: 2011-03-07
• [Presentation] On indirect detection of functional hold-time violations using scan shift operations (2011)
  • Author(s): Tsuyoshi Iwagaki and Kewal K. Saluja
  • Organizer: IEICE Technical Report (FIIS-11-298)
  • Place of Presentation: Chiba
  • Year and Date: 2011-03-01
• [Presentation] An approach to test scheduling for asynchronous on-chip interconnects using integer programming (2010)
  • Author(s): 岩垣剛
  • Organizer: IEEE 11^<th> Workshop on RTL and High Level Testing
  • Place of Presentation: Shanghai Sheraton Hotel, Shanghai, China
  • Year and Date: 2010-12-06
• [Presentation] An approach to test scheduling for asynchronous on-chip interconnects using integer programming (2010)
  • Author(s): Tsuyoshi Iwagaki, Eiri Takeda and Mineo Kaneko
  • Organizer: Digest of Papers 11th IEEE Workshop on RTL and High Level Testing (WRTLT '10)
  • Place of Presentation: Shanghai (China)
  • Year and Date: 2010-12-01
• [Presentation] Test scheduling Algorithms for delay-insensitive chip area interconnects based on cone partitioning (2010)
  • Author(s): 岩垣剛
  • Organizer: 3^<rd> International Workshop on Impact of Low-Power Design on Test and Reliability
  • Place of Presentation: Hotel Don Giovanni, Prague, Czech Republic
  • Year and Date: 2010-05-28
• [Presentation] Test scheduling algorithms for delay-insensitive chip area interconnects based on cone partitioning (2010)
  • Author(s): Tsuyoshi Iwagaki, Eiri Takeda and Mineo Kaneko
  • Organizer: Proc. 3rd International Workshop on the Impact of Low-Power Design on Test and Reliability (LPonTR '10)
  • Place of Presentation: Prague (Czech republic)
  • Year and Date: 2010-05-01