Studies on Normal-Operation-Aware Accurate Delay Fault Testing for VLSIs
| Project/Area Number |
22700054
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | Oita University (2011-2013)
Nara Institute of Science and Technology (2010) |
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Principal Investigator |
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| Project Period (FY) |
2010-04-01 – 2014-03-31
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2013: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2012: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2011: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2010: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
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| Keywords | VLSIテスト技術 / 遅延故障テスト / テスト生成制約 / 組込み自己テスト / レジスタ転送レベル / 通常消費電力 / 通用消費電力 |
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| Research Abstract |
Since our life is dependent on computer systems, reliability of the computers is essential. To create reliable systems, very large scale integration circuits (VLSIs), which are the main components of the systems, need to be tested and the test quality must be improved considering their operating environment. Under this grant, for supporting normal-operation-aware testing, a method of test pattern and response delivery using normal operation, a method of thermal-uniformity-aware built-in self-test (BIST), a method of linear feedback shift register (LFSR) seed generation for high quality pseudo-random BIST, and a framework of constrained test generation to generate test and diagnosis patterns with desired properties have been developed.
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Report
(5 results)
Research Products
(30 results)
