Automatic Synthesis Method of High-Performance, Area-Efficient and Programmable Hardware
| Project/Area Number |
22760245
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | The University of Tokyo |
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Principal Investigator |
YOSHIDA Hiroaki 東京大学, 大規模集積システム設計教育研究センター, 特任助教 (10456163)
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| Project Period (FY) |
2010 – 2011
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| Project Status |
Completed (Fiscal Year 2011)
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| Budget Amount *help |
¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
Fiscal Year 2011: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2010: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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| Keywords | 電力効率 / 製造後機能修正 / Engineering Change Order(ECO) / 高位合成 / 集積回路 / 高電力効率 / 柔軟性 |
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| Research Abstract |
With the shorter time-to-market and the rising cost in SoC development, the demand for post-silicon programmability has been increasing. This research proposed a highly energy-efficient accelerator which enables post-silicon engineering change by a control patching mechanism. Then, this research proposed a patch compilation method from a given pair of an original design and a modified design. Experimental results demonstrated that the proposed accelerators offered high energy efficiency competitive to fixed-function accelerators and can achieve about 5X higher efficiency than the existing programmable accelerators.
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Report
(3 results)
Research Products
(15 results)
