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Side-Channel Attack Resistant Software Platforms for Multicore IoT Devices

Research Project

Project/Area Number 22K21276
Research Category

Grant-in-Aid for Research Activity Start-up

Allocation TypeMulti-year Fund
Review Section 1001:Information science, computer engineering, and related fields
Research InstitutionOsaka University

Principal Investigator

Nishikawa Hiroki  大阪大学, 大学院情報科学研究科, 助教 (90963538)

Project Period (FY) 2022-08-31 – 2024-03-31
Project Status Completed (Fiscal Year 2023)
Budget Amount *help
¥2,860,000 (Direct Cost: ¥2,200,000、Indirect Cost: ¥660,000)
Fiscal Year 2023: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2022: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Keywordsハードウェア・セキュリティ / サイドチャネル攻撃 / ハードウェア・セキュリティ攻撃 / 暗号アルゴリズム / 電力解析攻撃 / ランダムスケジューリング / 命令シャッフリング / セキュリティ / マルチコア / 組込みシステム
Outline of Research at the Start

Internet of Things (IoT) デバイスはフィジカル空間における様々なフィールド上に物理的に配置されるため,サイドチャネル攻撃の危険に常に晒されている.本研究では多くの IoT デバイスで用いられるマルチコアシステムに焦点を当て,並列処理の基盤技術を IoT セキュリティ対策手法として応用することで.物理セキュリティ攻撃に対して耐性を持つ IoT デバイスのソフトウェア基盤を構築する.本研究ではオペレーティングシステムの基盤技術を活用し,専用ハードウェアを開発せずともサイドチャネル攻撃に対して高い耐性が得られるソフトウェア基盤を構築する.

Outline of Final Research Achievements

In this study, we aimed to enhance the security of small devices connected to the Internet (IoT devices) and produced results concerning measures to protect information safely. Specifically, we evaluated the safety of AES encryption circuits designed using high-level synthesis technology, which automatically converts programming languages such as C and C++ into digital circuits. Furthermore, we extended and applied shuffling technology, which randomizes the order of functions within the round function during encryption, on AES operations performed on CPUs. This method processes information in an unpredictable order, making it more difficult for attackers to decrypt the encryption keys.

Academic Significance and Societal Importance of the Research Achievements

Society 5.0の実現に向け、Internet of Things (IoT) デバイスは様々なフィールドで普及しつつある。一方で、サイドチャネル攻撃などの物理セキュリティ攻撃の危険に晒されている。この脅威に対し、これまでに多数のセキュリティに特化した専用のハードウェアやソフトウェアが開発されてきたが、専用ハードウェアを刷新したり、セキュリティ対策 ソフトウェアを特別に開発したりするにはコストの増大が課題となる。本研究の意義は、オペレーティングシステムの基盤技術のみを活用することでサイドチャネル攻撃に強いソフトウェア基盤を提供できないか?」という問いに答えることにある。

Report

(3 results)
  • 2023 Annual Research Report   Final Research Report ( PDF )
  • 2022 Research-status Report
  • Research Products

    (12 results)

All 2024 2023 2022

All Journal Article (3 results) (of which Peer Reviewed: 3 results,  Open Access: 2 results) Presentation (9 results) (of which Int'l Joint Research: 7 results)

  • [Journal Article] Timing Issues on Power Side-Channel Leakage of AES Circuits Designed by High-Level Synthesis2024

    • Author(s)
      Yuto Miura, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama,
    • Journal Title

      International Journal of Reconfigurable and Embedded Systems (IJRES)

      Volume: -

    • Related Report
      2023 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Side Channel Power Analysis Resistance Evaluation of Masked Adders on FPGA2023

    • Author(s)
      Yilin Zhao, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama
    • Journal Title

      International Journal of Reconfigurable and Embedded Systems

      Volume: 12 (1) Issue: 1 Pages: 97-112

    • DOI

      10.11591/ijres.v12.i1.pp97-112

    • Related Report
      2023 Annual Research Report 2022 Research-status Report
    • Peer Reviewed / Open Access
  • [Journal Article] Empirical Analysis of Power Side-Channel Leakage of High-Level Synthesis Designed AES Circuits2023

    • Author(s)
      Takumi Mizuno, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama
    • Journal Title

      International Journal of Reconfigurable and Embedded Systems

      Volume: 12 Issue: 3 Pages: 305-319

    • DOI

      10.11591/ijres.v12.i3.pp305-319

    • Related Report
      2023 Annual Research Report
    • Peer Reviewed / Open Access
  • [Presentation] Impacts of Clock Frequency and Sampling Intervals on Power Side-Channel Leakage of AES Circuits2024

    • Author(s)
      Yuto Miura, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama
    • Organizer
      International Conference on Electronics, Information, and Communication (ICEIC)
    • Related Report
      2023 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Fast 32-Bit and 48-Bit Multipliers for FPGA2024

    • Author(s)
      Wakana Ohashi, Aoi Yamaguchi, Hiroki Nishikawa, Hiroyuki Tomiyama,
    • Organizer
      International Conference on Electronics, Information, and Communication (ICEIC)
    • Related Report
      2023 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 電力解析攻撃に対する複数の S-BOX を用いたオペレーション・シャッフリングに関する研究2024

    • Author(s)
      加治屋彰太, 西川広記, 吉田康太, 谷口一徹, 尾上孝雄
    • Organizer
      研究報告組込みシステム(EMB)
    • Related Report
      2023 Annual Research Report
  • [Presentation] Impacts of Clock Constraints on Side-Channel Leakage of HLS-Designed AES Circuits2023

    • Author(s)
      Yuto Miura, Takumi Mizuno, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama
    • Organizer
      International Conference on Electronics, Information, and Communication (ICEIC)
    • Related Report
      2023 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Simulation-based Analysis of Power Side-Channel Leakage at Different Sampling Intervals2023

    • Author(s)
      Yuto Miura, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama
    • Organizer
      nternational Workshop on Advances in Networking and Computing (WANC) in conjunction with International Symposium on Computing and Networking (CANDAR)
    • Related Report
      2023 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 電力のサンプリング間隔がAES回路のサイドチャネルリーク量に与える影響の評価2023

    • Author(s)
      三浦佑斗, 西川広記, 孔祥博, 冨山宏之
    • Organizer
      情報処理学会組込みシステム研究会
    • Related Report
      2023 Annual Research Report
  • [Presentation] Impacts of Clock Constraints on Side-Channel Leakage of HLS-Designed AES Circuits2022

    • Author(s)
      Yuto Miura, Takumi Mizuno, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama
    • Organizer
      International Conference on Electronics, Information, and Communication (ICEIC)
    • Related Report
      2022 Research-status Report
    • Int'l Joint Research
  • [Presentation] Empirical Analysis of Side-Channel Attack Resistance of HLS-Designed AES Circuits,2022

    • Author(s)
      Takumi Mizuno, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama,
    • Organizer
      International Conference on Electronics, Information, and Communication (ICEIC)
    • Related Report
      2022 Research-status Report
    • Int'l Joint Research
  • [Presentation] Energy Consumption Reduction through Resource Allocation Using Docker2022

    • Author(s)
      Eiji Sugahara, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama
    • Organizer
      International Workshop on Advances in Networking and Computing (WANC)
    • Related Report
      2022 Research-status Report
    • Int'l Joint Research

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Published: 2022-09-01   Modified: 2025-01-30  

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