| Budget Amount *help |
¥18,590,000 (Direct Cost: ¥14,300,000、Indirect Cost: ¥4,290,000)
Fiscal Year 2014: ¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2013: ¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2012: ¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2011: ¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
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| Outline of Final Research Achievements |
We have studied various design methodology for dependable logic circuits by utilizing the model of PPCs (Partially Programmable Circuits) which contains LUTs. Our main research result is concerning circuits which can bypass some manufacturing faults with less overhead compared with conventional methods. Our research achievement includes (1) design methods of PPCs, (2) how to reduce the area cost of LUTs without changing the ability to bypass faults, (3) how to utilize PPCs for engineering change, (4) verification methods of PPCs, and (5) high-level synthesis with functional units by PPCs.
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