| Budget Amount *help |
¥19,500,000 (Direct Cost: ¥15,000,000、Indirect Cost: ¥4,500,000)
Fiscal Year 2013: ¥5,850,000 (Direct Cost: ¥4,500,000、Indirect Cost: ¥1,350,000)
Fiscal Year 2012: ¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2011: ¥8,840,000 (Direct Cost: ¥6,800,000、Indirect Cost: ¥2,040,000)
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| Research Abstract |
Power electronic circuits are widely expanding as energy-saving key technologies, however, a switching noise is generated because a switching element may repeat an on/off action at high frequency. Conventional methods to reduce a noise are post-installed noise filters, snubber elements, etc. in the main circuit, which lead to the increase in size or weight and the cost rise, and the methods had taken great time to it. This research is to reduce noise by means of the new circuit topology in a power electronics main circuit. The method of reducing the common-mode-noise current due to the parasitic capacitance of the semiconductor switch of a three phase inverter circuit and the internal parasitic capacitance in a motor and the noise reduction method in a totem pole type bridgeless power factor correction converter are described.
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