| Project/Area Number |
23360146
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tohoku University |
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Principal Investigator |
LEE KANGWOOK 東北大学, 未来科学技術共同研究センター, 教授 (90534503)
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| Co-Investigator(Kenkyū-buntansha) |
FUKUSHIMA Takafumi 東北大学, 未来科学技術共同研究センター, 准教授 (10374969)
TANAKA Tetsu 東北大学, 大学院・医工学研究科, 教授 (40417382)
BEA Jichel 東北大学, 未来科学技術共同研究センター, 助教 (40509874)
MURUGESAN Mariappan 東北大学, 未来科学技術共同研究センター, 産学官連携研究員 (10509699)
裴 艶麗 東北大学, 国際高等研究教育機構, 助教 (70451622)
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| Co-Investigator(Renkei-kenkyūsha) |
KOYANAGI Mitsumasa 東北大学, 未来科学技術共同研究センター, 教授 (60205531)
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| Project Period (FY) |
2011-04-01 – 2014-03-31
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥19,630,000 (Direct Cost: ¥15,100,000、Indirect Cost: ¥4,530,000)
Fiscal Year 2013: ¥5,460,000 (Direct Cost: ¥4,200,000、Indirect Cost: ¥1,260,000)
Fiscal Year 2012: ¥6,760,000 (Direct Cost: ¥5,200,000、Indirect Cost: ¥1,560,000)
Fiscal Year 2011: ¥7,410,000 (Direct Cost: ¥5,700,000、Indirect Cost: ¥1,710,000)
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| Keywords | 複合Siウェハ / ヘテロＣＭＯＳトランジスタ / セルフアセンブリー張り合わせ / 複合Ｓｉウェハ / セルフアセンブリー張り合わせる / ヘテロCMOSトランジスタ / 複合ウェハ |
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| Research Abstract |
We developed new technology for high-performance, low-power hetero-junction CMOS comprising InGaAs NMOS and Ge PMOS on a large-dia. Si wafer. Ge chips and InGaAs chips are precisely (<1um accuracy) and tightly bonded (20MPa) on a smooth surface roughness (Ra 0.5 angstrom) of P-TEOS hydrophilic area on a Si wafer by using self-assembly technology. Shallow p-n junction technologies of ion implantation and annealing condition for hetero-junction CMOS are established. We successfully implemented Ge and InGaAs photodiodes on a Si wafer by using these technologies. This study shows the opportunity to manufacture high-performance, low-power Ge/InGaAs hetero-junction CMOS device on an 8/12 inch Si wafer with low cost.
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