| Budget Amount *help |
¥19,240,000 (Direct Cost: ¥14,800,000、Indirect Cost: ¥4,440,000)
Fiscal Year 2013: ¥5,720,000 (Direct Cost: ¥4,400,000、Indirect Cost: ¥1,320,000)
Fiscal Year 2012: ¥6,890,000 (Direct Cost: ¥5,300,000、Indirect Cost: ¥1,590,000)
Fiscal Year 2011: ¥6,630,000 (Direct Cost: ¥5,100,000、Indirect Cost: ¥1,530,000)
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| Research Abstract |
Interconnect integrity was studied for three dimensional VLSI systems, with a special focus on the electrical coupling between through silicon vias (TSV) and a silicon substrate. A prototype chip of three dimensional (3D) chip stacking was developped, measured, and analyzed for the experimental and analytical understanding, and showed that power and substrate noise coupling in a 3D interconnect was strongly dependent on the physical placements of TSVs in a chip and the operating frequency of circuits in a 3D system as well. The measurements were performed by using on-chip noise monitor and on-chip noise emulator circuits. The analysis was theoretically pursuied with an equivalent circuit involving 3D interconnect systems and a silicon susbtrate. The measurements and analysis agree well with the frequency dependency of noise coupling in a 3D prototype VLSI chip. This work was under the international collaborative research agreements between IMEC (Belgium) and Kobe University (Japan).
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