Study on Interconnect Integrity in Three Dimensional VLSI Systems
| Project/Area Number |
23360156
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Kobe University |
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Principal Investigator |
NAGATA Makoto 神戸大学, 大学院システム情報学研究科, 教授 (40274138)
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| Co-Investigator(Kenkyū-buntansha) |
HIROSE Tetsuya 神戸大学, 大学院・工学研究科, 准教授 (70396315)
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| Project Period (FY) |
2011-04-01 – 2014-03-31
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥19,240,000 (Direct Cost: ¥14,800,000、Indirect Cost: ¥4,440,000)
Fiscal Year 2013: ¥5,720,000 (Direct Cost: ¥4,400,000、Indirect Cost: ¥1,320,000)
Fiscal Year 2012: ¥6,890,000 (Direct Cost: ¥5,300,000、Indirect Cost: ¥1,590,000)
Fiscal Year 2011: ¥6,630,000 (Direct Cost: ¥5,100,000、Indirect Cost: ¥1,530,000)
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| Keywords | 電子デバイス / 集積回路 / 三次元デバイス / シリコン基板ノイズ / 電源供給インテグリティ / 信号インテグリティ / 電源配線ネットワーク / シリコン貫通ビア / 電源ノイズ / 電源供給網 / 基板ノイズ / オンチップモニタ / ミックストシグナルVLSI / アンプ / 電源網 / A/D変換器 |
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| Research Abstract |
Interconnect integrity was studied for three dimensional VLSI systems, with a special focus on the electrical coupling between through silicon vias (TSV) and a silicon substrate. A prototype chip of three dimensional (3D) chip stacking was developped, measured, and analyzed for the experimental and analytical understanding, and showed that power and substrate noise coupling in a 3D interconnect was strongly dependent on the physical placements of TSVs in a chip and the operating frequency of circuits in a 3D system as well. The measurements were performed by using on-chip noise monitor and on-chip noise emulator circuits. The analysis was theoretically pursuied with an equivalent circuit involving 3D interconnect systems and a silicon susbtrate. The measurements and analysis agree well with the frequency dependency of noise coupling in a 3D prototype VLSI chip. This work was under the international collaborative research agreements between IMEC (Belgium) and Kobe University (Japan).
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Report
(4 results)
Research Products
(20 results)
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[Journal Article] Measurements and Analysis of Substrate Noise Coupling in TSV based 3D Integrated Circuits2014
Author(s)
Yuuki Araga, Makoto Nagata, Geert Van der Plas, Pol Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Gerald Beyer, Eric Beyne
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Journal Title
IEEE Transactions on Components, Packaging, and Manufacturing Technology
Volume: Vol. 4, No. 6
Pages: 1026-1037
Related Report
Peer Reviewed
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[Journal Article] In-Tier Diagnosis of Power Domains in 3D TSV Ics2012
Author(s)
Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne
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Journal Title
Proc. IEEE International 3D Systems Integration Conference
Volume: 7.2.1-7.2.4
Related Report
Peer Reviewed
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[Presentation] 三次元積層LSI チップにおける基板ノイズの層間評価2012
Author(s)
高木康将, 荒賀佑樹, 永田真, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Julien Ryckaert, Eric Beyne
Organizer
電子情報通信学会技術報告
Place of Presentation
札幌
Year and Date
2012-08-02
Related Report
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[Presentation] 三次元積層LSIチップにおける基板ノイズの層間評価2012
Author(s)
高木康将、荒賀佑樹、永田真、Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Julien Ryckaert, Eric Beyne
Organizer
電子情報通信学会集積回路研究会
Place of Presentation
札幌市
Related Report
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