| Budget Amount *help |
¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2012: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2011: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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| Research Abstract |
We proposed the high-speed functional test technique, and developed the processor architecture which realizes it. These purposes are development of the effective test technique in the quality LSI test field. The strong point of a processor is the high pliability and extendibility of high-speed pattern generation and a pattern. We evaluated by implementing a proposal processor in FPGA. The result showed the high-speed functional test performance equivalent to LSI tester. Since a functional test is used abundantly very much by the acceptance test of LSI, it is very important to advance this research and to develop a low cost test system. Research results of the two cases were presented at the international conference and the three cases were presented at the Japanese conference.
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