• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

A Study of a Tile-based NoC System using IPs and its Design

Research Project

Project/Area Number 23500069
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Computer system/Network
Research InstitutionWaseda University

Principal Investigator

WATANABE TAKAHIRO  早稲田大学, 理工学術院, 教授 (70230969)

Project Period (FY) 2011 – 2013
Project Status Completed (Fiscal Year 2013)
Budget Amount *help
¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000)
Fiscal Year 2013: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2012: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2011: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
KeywordsNoC / SoC / IP / アーキテクチャ / 低電力 / ルーティング / PCB / 自動配線アルゴリズム / SoC / PCB / キャッシュ / 低消費電力 / バス配線 / Intellectual Property / ネットワークオンチップ (NoC) / NoC構成手法 / システムオンチップ SoC / LSIアーキテクチャ / 設計自動化 / 低消費電力アーキテクチャ / 低消費電力キャッシュ / IP / ネットワークオンチップ
Research Abstract

NoC(Network on Chip) is one of a promising solution to implement the ultra large scale system with high performance on a chip. For improving the design efficiency of NoC, an IP-reused design method was proposed to implement a core in each tile, where design techniques for instruction-level customizable processor IP were developed and its design environment was constructed. Application-specific NoCs of Two- or Three-dimension were also discussed, and NoC architectures for high throughput, low latency and low power were explored and routing algorithms with high performance or fault-tolerancy were developed. Besides, to solve a signal-delay problem of the board-level system composed of NoCs and SoCs(System on Chip), several routing algorithm ware proposed and evaluated.

Report

(4 results)
  • 2013 Annual Research Report   Final Research Report ( PDF )
  • 2012 Research-status Report
  • 2011 Research-status Report
  • Research Products

    (49 results)

All 2014 2013 2012 2011 Other

All Journal Article (20 results) (of which Peer Reviewed: 20 results) Presentation (26 results) Remarks (3 results)

  • [Journal Article] A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency2014

    • Author(s)
      Xin Jiang, Lian Zeng,Takahiro Watanabe
    • Journal Title

      IPSJ Trans.SLDM

      Volume: 13 Pages: 1-9

    • NAID

      130004705275

    • Related Report
      2013 Annual Research Report
    • Peer Reviewed
  • [Journal Article] LVSの出力情報を活用した VLSI 電源配線幅の高速検証システム2013

    • Author(s)
      亀井智紀, 渡邊孝博, 川北真裕
    • Journal Title

      電子情報通信学会論文誌D

      Volume: Vol.J96-D, No.5 Pages: 1330-1337

    • NAID

      110009603597

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] An Efficient Algorithm for 3D NoC Architecture Optimization2013

    • Author(s)
      Xin Jiang, Ran Zhang and Takahiro Watanabe
    • Journal Title

      IPSJ Trans. System LSI Design Methodology (情報処理学会)

      Volume: 6 Pages: 34-41

    • NAID

      130003369388

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] LVSの出力情報を活用したVLSI電源配線幅の高速検証システム2013

    • Author(s)
      亀井智紀 渡邊孝博 川北真裕
    • Journal Title

      電子情報通信学会 論文誌D

      Volume: J96-D Pages: 1330-1337

    • NAID

      110009603597

    • Related Report
      2013 Annual Research Report 2012 Research-status Report
    • Peer Reviewed
  • [Journal Article] An Efficient Algorithm for 3D NoC Architecture Optimization2013

    • Author(s)
      Xin Jiang, Ran Zhang, Takahiro Watanabe
    • Journal Title

      IPSJ Trans. System LSI Design Methodology

      Volume: 6 Pages: 34-41

    • NAID

      130003369388

    • Related Report
      2012 Research-status Report
    • Peer Reviewed
  • [Journal Article] Region-oriented Placement Algorithm for Coarse-grained Power-gating FPGA Architecture2012

    • Author(s)
      C.Li, Y.Dong and T.Watanabe
    • Journal Title

      IEICE Trans Information and Systems

      Volume: E95-D, 2 Pages: 314-323

    • NAID

      10030610510

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] Region Oriented Routing FPGA Architecture for Dynamic Power Gating2012

    • Author(s)
      Ce Li, Yiping Dong, Takahiro Watanabe
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E95.A Issue: 12 Pages: 2199-2207

    • DOI

      10.1587/transfun.E95.A.2199

    • NAID

      10031161353

    • ISSN
      0916-8508, 1745-1337
    • Related Report
      2012 Research-status Report
    • Peer Reviewed
  • [Journal Article] Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture2012

    • Author(s)
      C.Li, Y.Dong and T.Watanabe
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E95-D Issue: 2 Pages: 314-323

    • DOI

      10.1587/transinf.E95.D.314

    • NAID

      10030610510

    • ISSN
      0916-8532, 1745-1361
    • Related Report
      2011 Research-status Report
    • Peer Reviewed
  • [Journal Article] A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction2011

    • Author(s)
      Jiongyao Ye, Yu Wan and Takahiro Watanabe
    • Journal Title

      IEICE Trans. Fundamentals of Electoronics, Communications and Computer Sciences

      Volume: E94-A, 12 Pages: 2639-2648

    • NAID

      10030533810

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] A Hybrid Layer- Multiplexing and Pipeline Architecture for Efficient FPGA-based Multilayer Neural Network2011

    • Author(s)
      Y.P.Dong, C.Li, Z.Lin and Takahiro Watanabe
    • Journal Title

      IEICE NOLTA

      Volume: E94-N, 10 Pages: 522-532

    • NAID

      130001225021

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] An Adaptive Various-width Data Cache for Low Power Design2011

    • Author(s)
      Jiongyao Ye, Yu Wan, Takahiro Watanabe
    • Journal Title

      IEICE

      Volume: E94-D Pages: 1539-1546

    • NAID

      10030192385

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] Analysis Before Starting an Access : A New Power-Efficient Instruction Fetch Mechanism2011

    • Author(s)
      Jiongyao Ye, Yingtao Hu, Takahiro Watanabe
    • Journal Title

      IEICE

      Volume: E94-D 7 Pages: 1398-1408

    • NAID

      10029805481

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction2011

    • Author(s)
      Jiongyao Ye, Yu Wan and Takahiro Watanabe
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E94-A Issue: 12 Pages: 2639-2648

    • DOI

      10.1587/transfun.E94.A.2639

    • NAID

      10030533810

    • ISSN
      0916-8508, 1745-1337
    • Related Report
      2011 Research-status Report
    • Peer Reviewed
  • [Journal Article] Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture2011

    • Author(s)
      C. Li, Y.P.Dong and T.Watanabe
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E94-A Issue: 12 Pages: 2519-2527

    • DOI

      10.1587/transfun.E94.A.2519

    • NAID

      10030533568

    • ISSN
      0916-8508, 1745-1337
    • Related Report
      2011 Research-status Report
    • Peer Reviewed
  • [Journal Article] A Hybrid Layer-Multiplexing and Pipeline Architecture for Efficient FPGA-based Multilayer Neural Network2011

    • Author(s)
      Y.P.Dong, C.Li, Z.Lin and Takahiro Watanabe
    • Journal Title

      IEICE NOLTA

      Volume: E94-N、10 Pages: 522-532

    • NAID

      130001225021

    • Related Report
      2011 Research-status Report
    • Peer Reviewed
  • [Journal Article] An Adaptive Various-Width Data Cache for Low Power Design2011

    • Author(s)
      Jiongyao Ye, Yu Wan and Takahiro Watanabe
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E94-D Issue: 8 Pages: 1539-1546

    • DOI

      10.1587/transinf.E94.D.1539

    • NAID

      10030192385

    • ISSN
      0916-8532, 1745-1361
    • Related Report
      2011 Research-status Report
    • Peer Reviewed
  • [Journal Article] Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism2011

    • Author(s)
      Jiongyao Ye, Yingtao Hu, Hongfeng Ding and Takahiro Watanabe
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E94-D Issue: 7 Pages: 1398-1408

    • DOI

      10.1587/transinf.E94.D.1398

    • NAID

      10029805481

    • ISSN
      0916-8532, 1745-1361
    • Related Report
      2011 Research-status Report
    • Peer Reviewed
  • [Journal Article] A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency

    • Author(s)
      Xin Jiang, Lian Zeng, Takahiro Watanabe
    • Journal Title

      IPSJ Trans.SLDM

      Volume: vol.13 (to appear)

    • NAID

      130004705275

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] Region Oriented Routing FPGA Architecture for Dynamic Power Gating

    • Author(s)
      Ce Li , Yiping Dong and Takahiro Watanabe
    • Journal Title

      IEICE Trans.Fudamentals

      Volume: vol.E95-A 12 Pages: 2199-2207

    • NAID

      10031161353

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Journal Article] Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture

    • Author(s)
      C. Li, Y.P.Dong and T.Watanabe
    • Journal Title

      IEICE Trans. Fundamentals of Electronics Communications and Computer Sciences

      Volume: E94-A, 12 Pages: 2519-2527

    • NAID

      10030533568

    • Related Report
      2013 Final Research Report
    • Peer Reviewed
  • [Presentation] Efficient Delay-matching Bus Routing by using Multi-layers2014

    • Author(s)
      Yang Tian, Ran Zhang, Takahiro Watanabe
    • Organizer
      Int. Conf. on Electronics Packaging
    • Place of Presentation
      Toyama
    • Related Report
      2013 Final Research Report
  • [Presentation] Flexible L1 Cache Optimization for a Low Power Embedded System2013

    • Author(s)
      Huatao ZHAO, Sijie YIN, Yuxin Sun, Takahiro WATANABE
    • Organizer
      2013 Int .Conf. Mechatronic Sciences, Electric Engineering and Computer
    • Place of Presentation
      Niiata
    • Related Report
      2013 Final Research Report
  • [Presentation] Adaptive Router with Predictor using Congestion Degree for 3D Network-on-Chip2013

    • Author(s)
      Lian Zeng, Xin Jiang, Takahiro Watanabe
    • Organizer
      Proc. 2013 Int. Soc Design Conf. (ISOCC)
    • Place of Presentation
      Busan
    • Related Report
      2013 Final Research Report
  • [Presentation] A Sorting-Based IO Connection Assignment for Flip-Chip Designs2013

    • Author(s)
      Ran Zhang, Xue Wei, Takahiro Watanabe
    • Organizer
      the 10th Int. Conf. ASIC (ASICON 2013)
    • Place of Presentation
      Shenzhen
    • Related Report
      2013 Final Research Report
  • [Presentation] Pseudo Dual Path Processing to Reduce the Branch Misprediction Penalty in Embedded Processors2013

    • Author(s)
      Huatao ZHAO, Jiongyao YE, Yuxin Sun, Takahiro WATANABE
    • Organizer
      The 10th Int. Conf. on ASIC
    • Place of Presentation
      Shenzhen
    • Related Report
      2013 Final Research Report
  • [Presentation] A Parallel Routing Method for Fixed Pins using Virtual Boundary2013

    • Author(s)
      Ran Zhang, Takahiro Watanabe
    • Organizer
      Proc. IEEE 2013 TENCON-Spring
    • Place of Presentation
      Sydney
    • Related Report
      2013 Final Research Report
  • [Presentation] A Parallel Routing Method for Fixed Pins using Virtual Boundary2013

    • Author(s)
      Zhang Ran and Takahiro Watanabe
    • Organizer
      TENCON Spring 2013
    • Place of Presentation
      Sydney
    • Related Report
      2012 Research-status Report
  • [Presentation] Flexible L1 Cache Optimization for a Low Power Embedded System2013

    • Author(s)
      Huatao ZHAO, Jiongyao YE, Takahiro WATANABE
    • Organizer
      情報処理学会第5回全国大会
    • Place of Presentation
      仙台
    • Related Report
      2012 Research-status Report
  • [Presentation] Rotational Display Problem for Array Reference in LSI Layout Data2012

    • Author(s)
      Tomoki Kamei, Takahiro Watanabe
    • Organizer
      ITC-CSCC 2012
    • Place of Presentation
      Sapporo
    • Related Report
      2012 Research-status Report
  • [Presentation] An Efficient Design Algorithm for Exploring Flexible Topologies in Custom Adaptive 3D NoCs for High Performance and Low Power2011

    • Author(s)
      Xin Jiang, Ran Zhang and Takahiro Watanabe
    • Organizer
      Proc. 2011 IEEE 9th Int.Conf.on ASIC (ASICON 2011)
    • Place of Presentation
      Beijin
    • Related Report
      2013 Final Research Report
  • [Presentation] New Power-aware Placement for Region based FPGA Architecture combined with Dynamic Power Gating by PCHM2011

    • Author(s)
      C.Li, Y.P.Dong and T. Watanabe
    • Organizer
      Proc.ISLPED'11 (Int'l Symp. Low Power Electronics Design)
    • Place of Presentation
      Fukuoka
    • Related Report
      2013 Final Research Report
  • [Presentation] New Power Efficient FPGA Design Combining with Region-Constrained Placement and Multiple Power Domains2011

    • Author(s)
      C. Li, Y.P. Dong, Takahiro Watanabe
    • Organizer
      Proc.IEEE NEWCAS'11 (IEEE 9th Int. Conf. New Circuits and Systems)
    • Place of Presentation
      Paris
    • Related Report
      2013 Final Research Report
  • [Presentation] A High Performance Digital Neural Processor Design by Network on Chip Architecture2011

    • Author(s)
      Y.Dong, Y.Li and Takahiro Watanabe
    • Organizer
      Proc. VLSI-DAT'11
    • Place of Presentation
      Hsinchu
    • Related Report
      2013 Final Research Report
  • [Presentation] New Power-aware Placement for Region based FPGA Architecture combined with Dynamic Power Gating by PCHM2011

    • Author(s)
      C.Li, Y.P.Dong and T. Watanabe
    • Organizer
      ISLPED'11 (Int'l Symp. Low Power Electronics Design)
    • Place of Presentation
      Fukuoka, Japan
    • Related Report
      2011 Research-status Report
  • [Presentation] New Power Efficient FPGA Design Combining with Region-Constrained Placement and Multiple Power Domains2011

    • Author(s)
      C. Li, Y.P. Dong and Takahiro Watanabe
    • Organizer
      IEEE NEWCAS’11 (IEEE 9th Int'l Conf. New Circuits and Systems)
    • Place of Presentation
      Bordeaux, France
    • Related Report
      2011 Research-status Report
  • [Presentation] A High Performance Digital Neural Processor Design by Network on Chip Architecture2011

    • Author(s)
      Y.Dong, Y.Li and Takahiro Watanabe
    • Organizer
      VLSI-DAT'11
    • Place of Presentation
      Hsinchu, Taiwan
    • Related Report
      2011 Research-status Report
  • [Presentation] Adaptive Router with Predictor using Congestion Degree for 3D Network-on-Chip

    • Author(s)
      Lian Zeng, Xin Jiang, Takahiro Watanabe
    • Organizer
      2013 International Soc Design Conference (ISOCC)
    • Place of Presentation
      Busan, Korea
    • Related Report
      2013 Annual Research Report
  • [Presentation] Adaptive Router with Predictor using Congestion Degree

    • Author(s)
      Lian Zeng, Takahiro Watanabe
    • Organizer
      電子情報通信学会 2013ソサイエティ大会
    • Place of Presentation
      Fukuoka
    • Related Report
      2013 Annual Research Report
  • [Presentation] Adaptive routing with congestion estimation based on G-table

    • Author(s)
      Zheng Gong,Lian Zeng,Takahiro Watanabe
    • Organizer
      電子情報通信学会 2014総合大会
    • Place of Presentation
      Niigata
    • Related Report
      2013 Annual Research Report
  • [Presentation] A Sorting-Based IO Connection Assignment for Flip-Chip Designs

    • Author(s)
      Ran Zhang, Xue Wei, Takahiro Watanabe
    • Organizer
      the 10th International Conference on ASIC (ASICON 2013)
    • Place of Presentation
      Shenzhen, China
    • Related Report
      2013 Annual Research Report
  • [Presentation] A Parallel Routing Method for Fixed Pins using Virtual Boundary

    • Author(s)
      Ran Zhang, Takahiro Watanabe
    • Organizer
      IEEE 2013 TENCON-Spring
    • Place of Presentation
      Sydney, Australia
    • Related Report
      2013 Annual Research Report
  • [Presentation] Efficient Delay-matching Bus Routing by using Multi-layers

    • Author(s)
      Yang Tian, Ran Zhang, Takahiro Watanabe
    • Organizer
      Int.Conf.on Electronics Packaging (ICEP 2014)
    • Place of Presentation
      Toyama
    • Related Report
      2013 Annual Research Report
  • [Presentation] Efficient Length-matching Bus Routing by using Multi-layers

    • Author(s)
      Yang TIAN, Ran ZHANG, Takahiro WATANABE
    • Organizer
      電気関係学会九州支部連合大会2013
    • Place of Presentation
      Kumamoto
    • Related Report
      2013 Annual Research Report
  • [Presentation] Flexible L1 Cache Optimization for a Low Power Embedded System

    • Author(s)
      Huatao ZHAO, Sijie YIN, Yuxin Sun, Takahiro WATANABE
    • Organizer
      2013 International Conference on Mechatronic Sciences, Electric Engineering and Computer
    • Place of Presentation
      Harbin, China
    • Related Report
      2013 Annual Research Report
  • [Presentation] Pseudo Dual Path Processing to Reduce the Branch Misprediction Penalty in Embedded Processors

    • Author(s)
      Huatao ZHAO, Jiongyao YE, Yuxin Sun, Takahiro WATANABE
    • Organizer
      10th International Conference on ASIC
    • Place of Presentation
      Shenzhen, China
    • Related Report
      2013 Annual Research Report
  • [Presentation] A Stack-based Solution for Alias Problem in Branch Prediction

    • Author(s)
      殷思杰,カドウ チョ,渡邊孝博
    • Organizer
      第76回情報処理学会全国大会
    • Place of Presentation
      Tokyo
    • Related Report
      2013 Annual Research Report
  • [Remarks] ホームページ

    • URL

      http://www.f.waseda.jp/watt/homepage/index_en.html

    • Related Report
      2013 Final Research Report
  • [Remarks] 渡邊研究室へようこそ (Welcome to Watanabe Lab.)

    • URL

      http://www.f.waseda.jp/watt/homepage/index_en.html

    • Related Report
      2013 Annual Research Report
  • [Remarks]

    • URL

      http://www.f.waseda.jp/watt/homepage/index_en.html

    • Related Report
      2011 Research-status Report

URL: 

Published: 2011-08-05   Modified: 2019-07-29  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi