A Study of a Tile-based NoC System using IPs and its Design
| Project/Area Number |
23500069
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Waseda University |
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Principal Investigator |
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| Project Period (FY) |
2011 – 2013
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000)
Fiscal Year 2013: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2012: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2011: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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| Keywords | NoC / ＳｏＣ / ＩＰ / アーキテクチャ / 低電力 / ルーティング / ＰＣＢ / 自動配線アルゴリズム / SoC / PCB / キャッシュ / 低消費電力 / バス配線 / Intellectual Property / ネットワークオンチップ (NoC) / NoC構成手法 / システムオンチップ SoC / LSIアーキテクチャ / 設計自動化 / 低消費電力アーキテクチャ / 低消費電力キャッシュ / IP / ネットワークオンチップ |
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| Research Abstract |
NoC(Network on Chip) is one of a promising solution to implement the ultra large scale system with high performance on a chip. For improving the design efficiency of NoC, an IP-reused design method was proposed to implement a core in each tile, where design techniques for instruction-level customizable processor IP were developed and its design environment was constructed. Application-specific NoCs of Two- or Three-dimension were also discussed, and NoC architectures for high throughput, low latency and low power were explored and routing algorithms with high performance or fault-tolerancy were developed. Besides, to solve a signal-delay problem of the board-level system composed of NoCs and SoCs(System on Chip), several routing algorithm ware proposed and evaluated.
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Report
(4 results)
Research Products
(49 results)
