| Budget Amount *help |
¥5,070,000 (Direct Cost: ¥3,900,000、Indirect Cost: ¥1,170,000)
Fiscal Year 2013: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2012: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2011: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
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| Research Abstract |
In order to search for a floorplan of a 3D-LSI by using Simulated Annealing method, three representations: Stacked-Rectangular-Dissection, Multi-sequence, and FT-squeeze were proposed.
Moreover, we proposed Single-SP, which represents relative position of modules for each device layer by one sequence-pair and a sequence of numbers, and MOVE operations which have small variety of adjacent solutions. The effectiveness of the proposed representation and MOVE operations were confirmed by experimental comparisons.
Also, we focused on the diameter of the solution space and proposed a new construction method of solution space. And we verified effectiveness of the method by computer experiments.
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