Equivalence Checking for System-Level Designs Having Different Input-Output Timings
| Project/Area Number |
23700051
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | The University of Tokyo |
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Principal Investigator |
MATSUMOTO Takeshi 東京大学, 大規模集積システム設計教育研究センター, 助教 (40536140)
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| Project Period (FY) |
2011 – 2012
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2012: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2011: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Keywords | 等価性検証 / システムレベル設計 / 形式的検証 / 高位設計 |
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| Research Abstract |
In this work, design verification methods for embedded systems or VLSIs are studied. The purpose of design verification is to check whether a given design is correct or not and provide failing patterns if incorrect. We focus on equivalence checking of given two designs. Our target of verification is system-level design, which is a highly abstracted design level and has become widely applied recently. We proposed equivalence checking methods that can deal with different input/output timings between given two designs. In addition, we have developed a method to detect potentially equivalent internal variables in designs. The purposed of this work is to improve the ability of equivalence checking for system-level designs by those proposed methods.
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Report
(4 results)
Research Products
(12 results)
