| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2013: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2011: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Outline of Final Research Achievements |
We proposed a low-latency and high-throughput lossless compression algorithm, named periodic pattern coding, to improve the memory access performance of super parallel processors. Compression ratio of the proposed method is evaluated by a GPU simulator, and result showed that the proposed method has higher compression ratio compared to conventional compression methods. Also, evaluations of the cache miss ratio and instructions per cycle (IPC) demonstrated that the proposed method is effective to improve the processor performance. Compression/decompression circuits are designed using hardware description language, and results showed that the circuit provides high processing throughputs.
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