| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2013: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2011: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
|
|---|
| Research Abstract |
To tolerate the increasing electronic error, the traditional way in microprocessor is to use dual or triple modular redundancy for high-dependable execution, which does not show good energy efficiency. In this research, targeting at a low-power high-performance fault toleration, the following points have been carried out: 1. A fusion of temporal and spatial redundancy: 2. A non-TMR based scheme to locate the permanent failure; (3) Architectural method to aid NBTI effects. The results of this research have been published in 7 journal papers and 9 international conference papers with referee.
|
