Improvement of the quality and coverage for delay testing of high speed LSI
| Project/Area Number |
23700061
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Kyushu Institute of Technology |
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Principal Investigator |
MIYASE Kohei 九州工業大学, 大学院・情報工学研究院, 助教 (30452824)
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| Project Period (FY) |
2011 – 2012
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| Project Status |
Completed (Fiscal Year 2012)
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| Budget Amount *help |
¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
Fiscal Year 2012: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2011: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
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| Keywords | VLSI設計技術 |
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| Research Abstract |
We could develop a delay testing method to improve the quality and coverage for high speed LSI. The method could combine the high quality testing technique and high coverage testing technique within a small increase of test application time. Also, we could develop a technique to visualize the coverage of selected paths with our own software. We have published this work in one Japanese workshop and two international workshops.
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Report
(3 results)
Research Products
(4 results)
