Energy-Aware HW/SW Co-Design Method for Fine-Grained Power-Gated VLIW Processors
| Project/Area Number |
23700067
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system/Network
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| Research Institution | Ritsumeikan University |
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Principal Investigator |
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| Project Period (FY) |
2011 – 2013
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2012: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2011: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | HW/SW協調設計 / VLIW型プロセッサ / 低消費電力化 |
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| Research Abstract |
Power gating is well-known technique to reduce the leakage energy drastically, but it suffers from performance penalty. This research proposes leakage energy aware HW/SW co-design method for fine-grained power gated VLIW processors. VLIW processors have multiple instruction slots, and power gating is supposed to be applied to each functional units. This research proposes two methods: energy-aware instruction scheduling method and architecture exploration method. Energy-aware instruction scheduling method optimizes the instruction scheduling taking into account power gating effects. Architecture exploration method tries to find Pareto optimal architecture candidates, and especially focuses on the number of functional unit and instruction assignment. Experimental results show the efficiency of proposed methods.
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Report
(4 results)
Research Products
(17 results)
