• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

Energy-Aware HW/SW Co-Design Method for Fine-Grained Power-Gated VLIW Processors

Research Project

Project/Area Number 23700067
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeMulti-year Fund
Research Field Computer system/Network
Research InstitutionRitsumeikan University

Principal Investigator

TANIGUCHI Ittetsu  立命館大学, 理工学部, 助教 (40551453)

Project Period (FY) 2011 – 2013
Project Status Completed (Fiscal Year 2013)
Budget Amount *help
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2012: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2011: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
KeywordsHW/SW協調設計 / VLIW型プロセッサ / 低消費電力化
Research Abstract

Power gating is well-known technique to reduce the leakage energy drastically, but it suffers from performance penalty. This research proposes leakage energy aware HW/SW co-design method for fine-grained power gated VLIW processors. VLIW processors have multiple instruction slots, and power gating is supposed to be applied to each functional units. This research proposes two methods: energy-aware instruction scheduling method and architecture exploration method. Energy-aware instruction scheduling method optimizes the instruction scheduling taking into account power gating effects. Architecture exploration method tries to find Pareto optimal architecture candidates, and especially focuses on the number of functional unit and instruction assignment. Experimental results show the efficiency of proposed methods.

Report

(4 results)
  • 2013 Annual Research Report   Final Research Report ( PDF )
  • 2012 Research-status Report
  • 2011 Research-status Report
  • Research Products

    (17 results)

All 2014 2013 2012 2011 Other

All Journal Article (1 results) (of which Peer Reviewed: 1 results) Presentation (16 results)

  • [Journal Article] Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path2014

    • Author(s)
      I. Taniguchi、K. Aoki、H. Tomiyama、P. Raghavan、F. Catthoor、M. Fukui
    • Journal Title

      IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

      Volume: E97.A Issue: 2 Pages: 606-615

    • DOI

      10.1587/transfun.E97.A.606

    • NAID

      130003394754

    • ISSN
      0916-8508, 1745-1337
    • Related Report
      2013 Annual Research Report 2013 Final Research Report
    • Peer Reviewed
  • [Presentation] A Basic-Block Level Optimistic Energy Estimation for Power-Gated VLIW Data-Path Model2013

    • Author(s)
      S. Nakamura、I. Taniguchi、H. Tomiyama、M. Fukui
    • Organizer
      The 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013)
    • Place of Presentation
      ホテル札幌ガーデンパレス(北海道)
    • Year and Date
      2013-10-22
    • Related Report
      2013 Final Research Report
  • [Presentation] GA-based Architecture Exploration Method for Low Energy VLIW Data-Path Model2013

    • Author(s)
      K. Aoki、I. Taniguchi、H. Tomiyama、M. Fukui
    • Organizer
      International Symposium on Communications and Information Technologies (ISCIT)
    • Place of Presentation
      Samui Island (Thailand)
    • Year and Date
      2013-09-05
    • Related Report
      2013 Final Research Report
  • [Presentation] A New Metric for Basic-Block Level Rough Energy Estimation for Power-Gated VLIW Data-Path Model2013

    • Author(s)
      S. Nakamura、K. Aoki、M. Uchida、I. Taniguchi、H. Tomiyama、M. Fukui
    • Organizer
      International Symposium on Communications and Information Technologies (ISCIT)
    • Place of Presentation
      Samui Island (Thailand)
    • Year and Date
      2013-09-05
    • Related Report
      2013 Final Research Report
  • [Presentation] 細粒度電源管理を考慮した基本ブロックレベル消費エネルギー推定手法2013

    • Author(s)
      中村駿介、青木康平、内田充哉、谷口一徹、冨山宏之、福井正博
    • Organizer
      情報処理学会SLDM研究会
    • Place of Presentation
      対馬市交流センター(長崎県)
    • Year and Date
      2013-03-13
    • Related Report
      2013 Final Research Report
  • [Presentation] Energy-Aware SA-based Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors2012

    • Author(s)
      M. Uchida、I. Taniguchi、H. Tomiyama、M. Fukui
    • Organizer
      International SoC Design Conference (ISOCC2012)
    • Place of Presentation
      Jeju Island (Korea)
    • Year and Date
      2012-11-06
    • Related Report
      2013 Final Research Report
  • [Presentation] An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating2011

    • Author(s)
      I. Taniguchi、M. Uchida、H. Tomiyama、M. Fukui、P. Raghavan、F. Catthoor
    • Organizer
      14th EUROMICRO Conference on Digital System Design (DSD2011)
    • Place of Presentation
      Oulu (Finland)
    • Year and Date
      2011-09-02
    • Related Report
      2013 Final Research Report
  • [Presentation] Architecture Optimization based on a Branch-and-Bound Strategy for Low-Energy Embedded VLIW Processors2011

    • Author(s)
      K. Aoki、I. Taniguchi、H.Tomiyama、M. Fukui
    • Organizer
      International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2011)
    • Place of Presentation
      Gyeongjoo (Korea)
    • Year and Date
      2011-06-20
    • Related Report
      2013 Final Research Report
  • [Presentation] Energy-Aware ILP-based Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors2011

    • Author(s)
      M. Uchida、I. Taniguchi、H. Tomiyama、M. Fukui
    • Organizer
      International Technical Conference on Circuits/Systems,Computers and Communications (ITC-CSCC2011)
    • Place of Presentation
      Gyeongjoo (Korea)
    • Year and Date
      2011-06-20
    • Related Report
      2013 Final Research Report
  • [Presentation] Energy-Aware ILP-based Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors2011

    • Author(s)
      Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Masahiro Fukui
    • Organizer
      International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2011)
    • Place of Presentation
      Gyeongjoo, Korea
    • Related Report
      2011 Research-status Report
  • [Presentation] Architecture Optimization based on a Branch-and-Bound Strategy for Low-Energy Embedded VLIW Processors2011

    • Author(s)
      Kohei Aoki, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Masahiro Fukui
    • Organizer
      International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2011)
    • Place of Presentation
      Gyeongjoo, Korea
    • Related Report
      2011 Research-status Report
  • [Presentation] An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating2011

    • Author(s)
      Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui, Praveen Raghavan, Francky Catthoor
    • Organizer
      14th EUROMICRO Conference on Digital System Design (DSD2011)
    • Place of Presentation
      Oulu, Finland
    • Related Report
      2011 Research-status Report
  • [Presentation] A Basic-Block Level Optimistic Energy Estimation for Power-Gated VLIW Data-Path Model

    • Author(s)
      Shunsuke Nakamura, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui
    • Organizer
      The 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2013)
    • Place of Presentation
      ホテル札幌ガーデンパレス(北海道)
    • Related Report
      2013 Annual Research Report
  • [Presentation] GA-based Architecture Exploration Method for Low Energy VLIW Data-Path Model

    • Author(s)
      Kohei Aoki, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui
    • Organizer
      International Symposium on Communications and Information Technologies (ISCIT)
    • Place of Presentation
      Samui Island, Thailand
    • Related Report
      2013 Annual Research Report
  • [Presentation] A New Metric for Basic-Block Level Rough Energy Estimation for Power-Gated VLIW Data-Path Model

    • Author(s)
      Shunsuke Nakamura, Kohei Aoki, Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui
    • Organizer
      International Symposium on Communications and Information Technologies (ISCIT)
    • Place of Presentation
      Samui Island, Thailand
    • Related Report
      2013 Annual Research Report
  • [Presentation] Energy-Aware SA-based Instruction Scheduling for Fine-Grained Power-Gated VLIW Processors

    • Author(s)
      Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, and Masahiro Fukui
    • Organizer
      International SoC Design Conference (ISOCC2012)
    • Place of Presentation
      Jeju, Korea
    • Related Report
      2012 Research-status Report
  • [Presentation] 細粒度電源管理を考慮した基本ブロックレベル消費エネルギー推定手法

    • Author(s)
      中村駿介, 青木康平, 内田充哉, 谷口一徹, 冨山宏之, 福井正博
    • Organizer
      情報処理学会 システムLSI設計技術研究発表会
    • Place of Presentation
      対馬市交流センター 長崎県
    • Related Report
      2012 Research-status Report

URL: 

Published: 2011-08-05   Modified: 2019-07-29  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi