Development of local-strain technology for crystalline Ge and its application to transistors
| Project/Area Number |
23760017
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Applied materials science/Crystal engineering
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| Research Institution | Kyushu University |
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Principal Investigator |
WANG Dong 九州大学, 総合理工学研究院, 准教授 (10419616)
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| Project Period (FY) |
2011 – 2012
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| Project Status |
Completed (Fiscal Year 2012)
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| Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2012: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2011: ¥3,380,000 (Direct Cost: ¥2,600,000、Indirect Cost: ¥780,000)
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| Keywords | 解析・評価 / 半導体物性 / 電子・電気材料 / 先端機能デバイス / ゲルマニウム(Ge) / 歪み印加 / MOSFET / 高移動度チャネル / ゲルマニウム（Ge） |
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| Research Abstract |
To establish the technology of a strained Ge channel, after stressor formation, the dependences of strain on geometric and thermal treatment parameters were investigated by Raman spectroscopy. Defect generation, transformation, and distribution were also clarified by photoluminescence. To fabricate Ge-MOSFET, an ultra-thin SiO2/GeO2bilayer Ge-surface passivation method was developed without vacuum breaking, which showed a low interface states density (Dit) in the same degree of that for SiO2/Si. To eliminate the influence of slow-traps in the SiO2/GeO2structure, a deep level transient spectroscopy method was developed with optimized bias condition at each fixed-temperature, by which an accurate Ditevaluation was performed for GeO2/Ge. According to the result of strain evaluation, a good-quality Ge-MOSFET should be fabricated at a temperature less than 500 oC. Therefore, a low-temperature process was developed for Ge-MOSFET fabrication, by which the operation of Ge transistors was approved. Particularly, the channel mobility of p-MOSFET was four times higher than that of a Si transistor.
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Report
(3 results)
Research Products
(69 results)
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[Presentation] Contact Formations for Schottky Source/Drain Ge-CMOS2013
Author(s)
Hiroshi Nakashima, Keisuke Yamamoto, Dong Wang
Organizer
6th International Workshop on New Group IV Semiconductor Nanoelectronics and JSPS Core-to Core Program Joint Seminar, "Atomically Controlled Processsing for Ultralarge Scale Integration"
Place of Presentation
6th International Workshop on New Group IV Semiconductor Nanoelectronics and JSPS Core-to Core Program Joint Seminar, "Atomically Controlled Processsing for Ultralarge Scale Integration"
Year and Date
2013-02-23
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[Presentation] Contact Formations for Schottky Source/Drain Ge-CMOS
Author(s)
Hiroshi Nakashima, Keisuke Yamamoto, and Dong Wang
Organizer
6th International Workshop on New Group IV Semiconductor Nanoelectronics and JSPS Core-to Core Program Joint Seminar, “Atomically Controlled Processsing for Ultralarge Scale Integration”
Place of Presentation
Tohoku University, Sendai, JAPAN
Related Report
Invited
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