Optimization Techniques for Wireless 3-D Network-on-Chips

• Project/Area Number: 23800053
• Research Category: Grant-in-Aid for Research Activity Start-up
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: Keio University
• Principal Investigator: MATSUTANI Hiroki 慶應義塾大学, 理工学部, 専任講師 (70611135)
• Project Period (FY): 2011 – 2012
• Project Status: Completed (Fiscal Year 2012)
• Budget Amount: ¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000); Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000); Fiscal Year 2011: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
• Keywords: 計算機アーキテクチャ / 結合網 / Network-on-Chip / ルーティング / 3次元IC / 計算機 / ネットワーク / NoC / メニーコア / 3次元積層

Research Abstract

Three-dimensional integration enables us to build a custom LSI system to by stacking necessary chips without remaking LSI mask patterns. This research investigates optimization techniques for the wireless 3-D Network-on-Chip that integrates intra-chip net

Research Products

• [Journal Article] 3-D NoC with Inductive-Coupling Links for Building-Block SiPs (2012)
  • Author(s): Yasuhiro Take
  • Journal Title: IEEE Transactions on Computers (TC) Volume: (掲載決定) Issue: 3 Pages: 748-763
  • DOI: 10.1109/tc.2012.249
  • Peer Reviewed / Open Access
• [Presentation] A Case for Wireless 3D NoCs for CMPs (2013)
  • Author(s): Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
  • Organizer: Wireless 3D NoCs for CMPs", Proc. of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13)
  • Place of Presentation: Yokohama
• [Presentation] A Case for Wireless 3D NoCs for CMPs (2013)
  • Author(s): Hiroki Matsutani
  • Organizer: 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13)
  • Place of Presentation: Yokohama
• [Presentation] Vertical Link On/Off Control Methods for Wireless 3-D NoCs (2012)
  • Author(s): Hao Zhang, et.al.
  • Organizer: International Conference on Architecture of Computing Systems (ARCS'12)
  • Place of Presentation: Munich, Germany
  • Year and Date: 2012-03-02
• [Presentation] A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs (2012)
  • Author(s): Hiroki Matsutani, et.al.
  • Organizer: Asia and South Pacific Design Automation Conference (ASP-DAC'12)
  • Place of Presentation: Sydney, Australia
  • Year and Date: 2012-02-01
• [Presentation] 多電源可変パイプラインルータにおける電源ドメインサイズの解析 (2012)
  • Author(s): 中村武雄, 他
  • Organizer: 電子情報通信学会技術研究報告CPSY2011-62,Vol.111,No.398
  • Place of Presentation: 横浜,日本
  • Year and Date: 2012-01-25
• [Presentation] A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs (2012)
  • Author(s): Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
  • Organizer: Proc. of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC'12)
  • Place of Presentation: Sydney, Australia
• [Remarks] 受賞:"Best Paper Award", The 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13).(投稿311件、受賞は2件)
  • URL: http://www.arc.ics.keio.ac.jp/~matutani/index.j.html
• [Remarks] ニュース:"【ASP-DAC 2013】3次元実装LSIや温度・電力シミュレーションの一般講演に注目", 日経BP社Tech-On!, 2013年1月20日.
• [Remarks] "【ASP-DAC 2013続報】ダイの差し替えが容易な3次元IC、慶大らが無線接続技術の応用で提案", 日経BP社Tech-On!, 2013年3月12日.
• [Remarks] 研究者のウェブページ
  • URL: http://www.arc.ics.keio.ac.jp/~matutani/
• [Remarks]
  • URL: http://www.ny.ics.keio.ac.jp/~matutani
• [Patent(Industrial Property Rights)] 三次元集積電気回路の配線構造及びそのレイアウト方法 (2012)
  • Inventor(s): 鯉渕 道紘、松谷 宏紀
  • Industrial Property Rights Holder: 大学共同利用機関法人情報・システム研究機構
  • Filing Date: 2012-06-29