Optimization Techniques for Wireless 3-D Network-on-Chips
| Project/Area Number |
23800053
|
|---|
| Research Category |
Grant-in-Aid for Research Activity Start-up
|
| Allocation Type | Single-year Grants |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | Keio University |
|---|
Principal Investigator |
|
|---|
| Project Period (FY) |
2011 – 2012
|
| Project Status |
Completed (Fiscal Year 2012)
|
| Budget Amount *help |
¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000)
Fiscal Year 2012: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2011: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
|
|---|
| Keywords | 計算機アーキテクチャ / 結合網 / Network-on-Chip / ルーティング / 3次元IC / 計算機 / ネットワーク / NoC / メニーコア / 3次元積層 |
|---|
| Research Abstract |
Three-dimensional integration enables us to build a custom LSI system to by stacking necessary chips without remaking LSI mask patterns. This research investigates optimization techniques for the wireless 3-D Network-on-Chip that integrates intra-chip net
|
Report
(3 results)
Research Products
(13 results)
-
-
[Presentation] A Case for Wireless 3D NoCs for CMPs2013
Author(s)
Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
Organizer
Wireless 3D NoCs for CMPs", Proc. of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC'13)
Place of Presentation
Yokohama
Related Report
-
-
-
-
-
-
-
-
-
-
-
