| Project/Area Number |
23K19979
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| Research Category |
Grant-in-Aid for Research Activity Start-up
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| Allocation Type | Multi-year Fund |
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| Review Section |
1001:Information science, computer engineering, and related fields
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| Research Institution | Keio University |
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Principal Investigator |
魏 凱傑 慶應義塾大学, 理工学研究科(矢上), 特任助教 (90983867)
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| Project Period (FY) |
2023-08-31 – 2025-03-31
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| Project Status |
Granted (Fiscal Year 2023)
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| Budget Amount *help |
¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
Fiscal Year 2024: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2023: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | state vector, / HLS, / Qulacs, / Serial ATA, / FPGA, / quantum computer, / storage system, / simulation / FPGA / Quantum simulation / SATA / HLS / Qulacs |
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| Outline of Research at the Start |
Large-scale state vector simulator is hard to handle mainly works on HPCs. An effective quantum computer simulator using edge device is necessary for quantum’s research. Trefoil design is to solve the bottleneck problem of the memory bomb, and quantum gate design boosts the simulation's performance.
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| Outline of Annual Research Achievements |
In Y2023, the applicant implements the initial design of Trefoil-Qulacs. First, I finished the high-level synthesis (HLS) designs of the Hadamard, Pauli-Z, Phase, Controlled-NOT, and Unitary Matrix using Vitis HLS 2022.2 based on Qulacs. In this stage, I emphasize the algorithm optimization using HLS techniques. To enhance the robustness of the Trefoil-Qulacs, I redesigned the referred quantum gate algorithm, which considers the SATA disk characteristics with the FPGA platform. The Trefoil can construct any quantum circuit with the combination of designed IPs.
Furthermore, I verified the designed IPs on the Trefoil storage subsystem after the overall system's implementation using Vivado 2022.2. Since one IP instance has to correspond to a SATA disk, 32 IPs should be involved in the target design. There is a great challenge to on-chip memory resources. According to the evaluations using the physical board, the system can realize 43-qubit quantum circuit simulation using 32 8TB SATA disks, which can only achieved by supercomputers till now. However, the system needs more long-term simulations than supercomputer simulations due to the inefficient communication between SATA disks and FPGA. During the preparation for demonstrations at academic conferences (FPT, MCSoC) and Technique EXPO, I created two more IPs in the substitution of LiteX proposed in the research plan, which enables a more friendly environment for quantum circuit simulation using display. Regarding these two IPs, one is for communication with SATA disks, and the other is in the place of the CPU using Rasberry Pi.
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| Current Status of Research Progress |
Current Status of Research Progress
1: Research has progressed more than it was originally planned.
Reason
According to the research plan, the Trefoil storage subsystem was initially devised to function on XILINX Ultrascale XKU060 and establish a connection with 16 SATA disks. However, after its implementation, I realized that the system design needed to be more stable to handle the given workload, and the on-chip resources needed to be improved. In light of this, I have changed the platform, and after a thorough analysis, the FPGA chip was upgraded to XILINX Ultrscale+ XCKU15P. The new platform can connect with 32 SATA disks and has undergone rigorous testing to ensure its robustness and stability, thus ensuring optimal efficiency.
Between July and October, I redesign the IPs by customizing the on-chip resources. To ensure the system was reliable and efficient, I moved away from relying solely on simulation results. Instead, I began implementing experiments on the actual platform. After finishing the initial implementation of the whole system on the new Trefoil storage subsystem, I presented several demonstrations at academic conferences, including FPT and MCSoC, to demonstrate the system's capabilities. During a press statement in December, I improved the system's reliability and provided a more user-friendly environment that enables easy access to the system. To effectively control and confirm the functionality of the Trefoil storage subsystem, a Raspberry Pi is connected to the FPGA's GPIO working as CPU part. Additionally, the proposed system can connect with a portable display. Users can interactively visualize the simulation results with a Python-based graphical interface.
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| Strategy for Future Research Activity |
According to my two-year research plan, I put great effort into system optimization and research publication in Y2024. According to our analysis of the system time consumption, the data communication between SATA disks and FPGA dominates the simulation. Based on the current system's design. I have to exploit the possibility of pipelining the process of reading and computation to boost the target system's performance. Thus, I will spend three months (April~June) optimizing the design instead of focusing on the computation part. However, as described previously, each designed IP has to correspond to a SATA disk. Thus, 32 Qulacs IPs are involved in the system design. I have to control the resource utilization of each IP around 3% with ensuring the construction of a full-geared system connecting with 32 SATA disks, which challenges the limited on-chip resource. A dedicated resource allocation is necessary for Trefoil-Qulacs. I target a fully optimized system whose time consumption only concerns the communication between SATA disks and FPGA. On the other hand, regarding the system evaluation and verification, I will check the simulation results from the GUI interface created in Y2023 and the simulation in Vitis HLS 2022.2.2.
As the final step, I will summarize the system in a journal paper, including detailed system designs and performance evaluations. Unlike the original proposal, the journal paper focuses on implementing the Qulacs-Trefoil design with the Trefoil storage subsystem connecting with 32 SATA disks. I will further improve the evaluation results during this process.
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