| Budget Amount *help |
¥36,530,000 (Direct Cost: ¥28,100,000、Indirect Cost: ¥8,430,000)
Fiscal Year 2014: ¥8,970,000 (Direct Cost: ¥6,900,000、Indirect Cost: ¥2,070,000)
Fiscal Year 2013: ¥9,620,000 (Direct Cost: ¥7,400,000、Indirect Cost: ¥2,220,000)
Fiscal Year 2012: ¥17,940,000 (Direct Cost: ¥13,800,000、Indirect Cost: ¥4,140,000)
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| Outline of Final Research Achievements |
A field effect transistor (FET) with a single-crystalline SrTiO3 (STO) channel of 2-20μm length and with a HfO2/Parylene-C double-layer gate insulator was developed in this research. Both the subthreshold swing (170mV/dec) and the carrier mobility (10cm2/Vs) at room temperature corroborate that the almost defect-free high-quality channel was created on STO. This is because the extremely inert Parylene-C is able to prevent the STO surface from deterioration, even though the thickness of Parylene-C is only 6nm. The sheet carrier density of the channel estimated by Hall effect measurement was 1e14/cm2; ten times as large as the value expected from the measured and invariant capacitance of the gate insulator. This unusual and surprising result can be explained by the appearance of negative capacitance, i.e., the negative compressibility of the quasi 2D metal on the STO surface when a correlation gap is closed at a kind of Mott transition. Unexpectedly, Mott FET was demonstrated on STO.
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