Research on high-performance and highly-dependable floating-point arithmetic unit arrays by contriving data representation
| Project/Area Number |
24300019
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Partial Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kyoto University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
TAKAGI Kazuyoshi 京都大学, 大学院情報学研究科, 准教授 (70273844)
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| Project Period (FY) |
2012-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥10,530,000 (Direct Cost: ¥8,100,000、Indirect Cost: ¥2,430,000)
Fiscal Year 2014: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
Fiscal Year 2013: ¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2012: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
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| Keywords | 算術演算回路 / 演算器アレイ / オンライン誤り検出 / (2)算術演算回路 |
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| Outline of Final Research Achievements |
We have studied methods for making a floating-point arithmetic unit (FPU) array high-performance and highly-dependable by contriving data representation in it. We have proposed methods for constructing concurrently error-detectable FPUs by parity prediction or partial duplication or residue checking, and a method for performing quasi-quadruple precision arithmetic by coupling two double precision floating-point fused multiply-adders. We also proposed a synthesis method of an array of processing elements consisting of an FPU and memory from a program comprising multiple loop structure and matrix operations. In addition, we have developed a simulator of an FPU array.
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Report
(4 results)
Research Products
(20 results)
