Application-Aware Highly Hierarchical Memory Architecture
| Project/Area Number |
24650018
|
|---|
| Research Category |
Grant-in-Aid for Challenging Exploratory Research
|
| Allocation Type | Single-year Grants |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | Tohoku University |
|---|
Principal Investigator |
KOBAYASHI Hiroaki 東北大学, サイバーサイエンスセンター, 教授 (40205480)
|
|---|
| Co-Investigator(Renkei-kenkyūsha) |
TAKIZAWA Hiroyuki 東北大学, 大学院情報科学研究科, 准教授 (70323996)
EGAWA Ryusuke 東北大学, サイバーサイエンスセンター, 准教授 (80374990)
|
|---|
| Project Period (FY) |
2012-04-01 – 2014-03-31
|
| Project Status |
Completed (Fiscal Year 2013)
|
| Budget Amount *help |
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2013: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2012: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
|
|---|
| Keywords | キャッシュメモリ / コンピュータアーキテクチャ / キャッシュパーティショニング / スレッドスケジューリング / メモリシステム / キャッシュ分割 / キャッシュバイパス / 電力最適化 / メモリサブシステム / キャッシュ管理機構 |
|---|
| Research Abstract |
The objective of this study is to establish a novel on-chip memory architecture that can provide necessary memory resources to running applications under the consideration of their behaviors and requirements regarding a memory subsystem on a multi-core processor.
In this study, we have developed a cache-resource management mechanism to realize energy-efficient high performance execution of multi-threaded applications on a multi-core processor. In cooperation with developed hardware functions of cache resizing and partitioning to reduce cache conflicts and maximize the efficiency of cache utilization, this mechanism can extract the potential of multi-core processors with a low-power consumption.
|
Report
(3 results)
Research Products
(12 results)
