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Automatic correction of hardware systems based on stream processing

Research Project

Project/Area Number 24650019
Research Category

Grant-in-Aid for Challenging Exploratory Research

Allocation TypeSingle-year Grants
Research Field Computer system/Network
Research InstitutionThe University of Tokyo

Principal Investigator

FUJITA Masahiro  東京大学, 学内共同利用施設等, 教授 (70323524)

Co-Investigator(Kenkyū-buntansha) MATSUMOTO Takeshi  東京大学, 大規模集積システム設計教育研究センター, 助教 (40536140)
Project Period (FY) 2012-04-01 – 2014-03-31
Project Status Completed (Fiscal Year 2013)
Budget Amount *help
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2013: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2012: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Keywordsストリーム処理 / 設計自動修復 / 高性能計算 / 多重表引 / メモリベース計算 / 自動設計修復 / ハイパフォーマンスコンピューティング / ストリーム処理化 / デバッグ支援技術
Research Abstract

In big data analysis, such as analyzing data on images, web manipulations, and sensor networks, same operations are repeated on each data item. Such big data are arranged as very long flows of data, called data stream, so that operations on different data items can be processed in parallel as highly pipelined operations. We have developed a new methodology where such data steams are processed by multiple retrievals of relatively small tables. As all tables are retrieved in parallel, we can expect huge parallelisms. It is also called memory-based computing in contrast to processor-based processing which is widely used today. We have developed a set of techniques by which the processing system can be automatically corrected even if some of the tables are disorder by adjusting other tables appropriately.

Report

(3 results)
  • 2013 Annual Research Report   Final Research Report ( PDF )
  • 2012 Research-status Report
  • Research Products

    (22 results)

All 2014 2013 2012 Other

All Journal Article (2 results) (of which Peer Reviewed: 1 results) Presentation (19 results) Remarks (1 results)

  • [Journal Article] SAT-based automatic rectification and debugging of combinational circuits with LUT insertions2014

    • Author(s)
      S. Jo, T. Matsumoto, and M. Fujita
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology

      Volume: Vol.7, February Issue Pages: 46-55

    • NAID

      130003394413

    • Related Report
      2013 Final Research Report
  • [Journal Article] SAT-based Automatic Rectification and Debugging of Combinational Circuits with LUT Insertions2014

    • Author(s)
      S. Jo, T. Matsumoto, M. Fujita
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology

      Volume: 7 Issue: 0 Pages: 46-55

    • DOI

      10.2197/ipsjtsldm.7.46

    • NAID

      130003394413

    • ISSN
      1882-6687
    • Related Report
      2013 Annual Research Report
    • Peer Reviewed
  • [Presentation] RTL datapath optimization using system-level transformations2014

    • Author(s)
      S. Ghandali, B. Alizadeh, M. Fujita, Z. Navabi
    • Organizer
      Proc. of International Symposium on Quality Electronic Design (ISQED'14)
    • Related Report
      2013 Final Research Report
  • [Presentation] アサーション自動生成とそのシミュレーションによる完全検証2014

    • Author(s)
      藤田昌宏, 城怜史, 松本剛史
    • Organizer
      組込技術とネットワークに関するワークショップ(ETNET2014)
    • Related Report
      2013 Final Research Report
  • [Presentation] プログラム可能データパスとSMTソルバーを利用した高位設計デバッグ手法2014

    • Author(s)
      松本剛史, 城怜史, 藤田昌宏
    • Organizer
      組込技術とネットワークに関するワークショップ(ETNET2014)
    • Related Report
      2013 Final Research Report
  • [Presentation] アサーション自動生成とそのシミュレーションによる完全検証2014

    • Author(s)
      藤田昌宏, 城怜史, 松本剛史
    • Organizer
      組込み技術とネットワークに関するワークショップ ETNET2014
    • Place of Presentation
      ICT文化センター, 沖縄
    • Related Report
      2013 Annual Research Report
  • [Presentation] Diagnosis and Correction of Buggy Hardware/Software with Formal Approaches2013

    • Author(s)
      M. Fujita
    • Organizer
      International Workshop on Design and Implementation of Formal Tools and Systems
    • Place of Presentation
      Portland, OR
    • Year and Date
      2013-10-19
    • Related Report
      2013 Final Research Report
  • [Presentation] Diagnosis and correction of buggy hardware/software with formal approaches2013

    • Author(s)
      M. Fujita
    • Organizer
      17th International Symposium on VLSI Design and Test
    • Related Report
      2013 Final Research Report
  • [Presentation] High Performance and Flexible Computing Systems with Electronic Design Automation2013

    • Author(s)
      M. Fujita
    • Organizer
      2013 IEEE International Conference on Electronic Measurement & Instruments
    • Related Report
      2013 Final Research Report
  • [Presentation] A Debugging Method for Gate Level Circuit Designs by Introducing Programmability2013

    • Author(s)
      K. Oshima, T. Matsumoto, and M. Fujita
    • Organizer
      Proc. of 21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC'13)
    • Related Report
      2013 Final Research Report
  • [Presentation] Hardware Implementation of BLTL Property Checkers for Acceleration of Statistical Model Checking2013

    • Author(s)
      K. Oshima, T. Matsumoto, and M. Fujita
    • Organizer
      Proc. of the International Conference on Computer-Aided Design (ICCAD'13)
    • Related Report
      2013 Final Research Report
  • [Presentation] Partial synthesis through sampling with and without specification2013

    • Author(s)
      M. Fujita, S. Jo, S. Ono, and T. Matsumoto
    • Organizer
      Proc. of the International Conference on Computer-Aided Design (ICCAD'13)
    • Related Report
      2013 Final Research Report
  • [Presentation] Debugging Processors with Advanced Features by Reprogramming LUTs on FPGA2013

    • Author(s)
      S. Jo, A.M. Gharehbaghi, T. Matsumoto, and M. Fujita
    • Organizer
      Proc. of the International Conference on Field-Programmable Technology (ICFPT)
    • Related Report
      2013 Final Research Report
  • [Presentation] A Debugging Method for Gate Level Circuit Designs by Introducing Programmability2013

    • Author(s)
      Kousuke Oshima, Takeshi Matsumoto, Masahiro Fujita
    • Organizer
      21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC '13)
    • Place of Presentation
      Istanbul, Turkey
    • Related Report
      2013 Annual Research Report
  • [Presentation] FOF: Functionally Observable Fault and its ATPG Techniques2013

    • Author(s)
      Masahiro Fujita, Takeshi Matsumoto, Satoshi Jo
    • Organizer
      21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC '13)
    • Place of Presentation
      Istanbul, Turkey
    • Related Report
      2013 Annual Research Report
  • [Presentation] Hardware Implementation of BLTL Property Checkers for Acceleration of Statistical Model Checking2013

    • Author(s)
      Kousuke Oshima, Takeshi Matsumoto, Masahiro Fujita
    • Organizer
      International Conference on Computer-Aided Design (ICCAD '13)
    • Place of Presentation
      San Jose, USA
    • Related Report
      2013 Annual Research Report
  • [Presentation] Partial synthesis through sampling with and without specification2013

    • Author(s)
      Masahiro Fujita, Satoshi Jo, Shohei Ono, Takeshi Matsumoto
    • Organizer
      International Conference on Computer-Aided Design (ICCAD '13)
    • Place of Presentation
      San Jose, USA
    • Related Report
      2013 Annual Research Report
  • [Presentation] Automatic Assertion Extraction in Gate-Level Simulation Using GPGPUs2012

    • Author(s)
      S. Ono, T. Matsumoto, and M. Fujita
    • Organizer
      Proc. of IEEE 30th International Conference on Computer Design
    • Related Report
      2013 Final Research Report
  • [Presentation] SAT-based automatic rectification and debugging of combinational circuits with LUT insertions2012

    • Author(s)
      S. Jo, T. Matsumoto, and M. Fujita
    • Organizer
      Proc. of IEEE 21st Asia Test Symposium
    • Related Report
      2013 Final Research Report
  • [Presentation] Automatic Assertion Extraction in Gate-Level Simulation Using GPGPUs2012

    • Author(s)
      Shohei Ono, Takeshi Matsumoto, Masahiro Fujita
    • Organizer
      IEEE 30th International Conference on Computer Design
    • Place of Presentation
      Montreal, Canada
    • Related Report
      2012 Research-status Report
  • [Presentation] SAT-based automatic rectification and debugging of combinational circuits with LUT insertions2012

    • Author(s)
      Satoshi Jo, Takeshi Matsumoto, Masahiro Fujita
    • Organizer
      IEEE 21st Asia Test Symposium
    • Place of Presentation
      新潟県朱鷺メッセ新潟コンベンションセンター
    • Related Report
      2012 Research-status Report
  • [Remarks]

    • URL

      http://www.cad.t.u-tokyo.ac.jp

    • Related Report
      2013 Final Research Report

URL: 

Published: 2013-05-31   Modified: 2019-07-29  

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