| Budget Amount *help |
¥12,220,000 (Direct Cost: ¥9,400,000、Indirect Cost: ¥2,820,000)
Fiscal Year 2015: ¥2,730,000 (Direct Cost: ¥2,100,000、Indirect Cost: ¥630,000)
Fiscal Year 2014: ¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000)
Fiscal Year 2013: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2012: ¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
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| Outline of Final Research Achievements |
In this research, we developed a software-based runtime architectural state optimization methodology for manycore processors. We applied proposed method to the optimized control of cache line replacement with helper-threading in order to mitigate the cache contention. In this technique, the helper-thread optimizes and indicates the policy of date insertion position within a cache set with a page granularity. The hardware performs data replacement accordingly. Based on the cycle accurate simulation, it is revealed that the proposed method achieves about 11% performance improvement over the conventional hardware-based cache replacement.
As an extension of this research, we studied and analyzed code optimization for FPGA accelerators. We proposed some code modification strategies for achieving higher performance in OpenCL based FPGA accelerations and showed that they are effective in some cases.
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