| Budget Amount *help |
¥3,380,000 (Direct Cost: ¥2,600,000、Indirect Cost: ¥780,000)
Fiscal Year 2013: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2012: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Research Abstract |
In the loop pipelining of high-level synthesis, the reduction of initiation intervals (IIs) is the key for high-performance. Traditional loop pipelining techniques, however, assume that the RAW dependences whose occurrences are unknown before execution always occur, resulting in increased IIs. In this research, we developed a technique that reduces IIs. In this technique, data written to memories in such dependences are also written to registers and the occurrences of the dependences are checked at runtime and the registers are accessed in case the dependences occur. We demonstrated that our technique reduces the numbers of execution cycles by 40% on average compared to the state-of-the-art loop pipelining technique.
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