Development of a High-level Synthesis System for Path Delay Testability

• Project/Area Number: 24700056
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Computer system/Network
• Research Institution: Kure National College of Technology
• Principal Investigator: YOSHIKAWA Yuki 呉工業高等専門学校, 機械工学分野, 准教授 (50453212)
• Project Period (FY): 2012-04-01 – 2015-03-31
• Project Status: Completed (Fiscal Year 2014)
• Budget Amount: ¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000); Fiscal Year 2014: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000); Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000); Fiscal Year 2012: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
• Keywords: 遅延テスト容易性 / 高位合成 / LSIのテスト / LSIの高信頼設計 / 遅延故障のテスト / LSIのCAD

Outline of Final Research Achievements

The increase in speed and performance of LSIs result in the increase in defective chips. To reduce the yield loss of produced chips and the cost of them, development of high quality and low cost test techniques is important. This research project has proposed a method of design (or high level synthesis) for testability at behavioral level.

Research Products

• [Journal Article] パス遅延故障の過剰テストを削減するためのテストパタン生成法 (2013)
  • Author(s): 古本圭, 吉川祐樹
  • Journal Title: 情報科学技術フォーラム講演論文集 Volume: RC-004 Pages: 85-88
  • Peer Reviewed
• [Presentation] 遅延故障のテスト容易性を指向した高位合成におけるスケジューリングに関する研究 (2015)
  • Author(s): 中谷夏主政, 吉川祐樹
  • Organizer: 総合大会 情報・システムソサイエティ特別企画
  • Place of Presentation: 立命館大学（滋賀県草津）
  • Year and Date: 2015-03-10 – 2015-03-13
• [Presentation] A Binding Method to Synthesize Path Delay Testable RTL Circuits (2014)
  • Author(s): Kei Furumoto and Yuki Yoshikawa
  • Organizer: Proc. 4rd International Symposium on Technology for Sustainability (ISTS)
  • Place of Presentation: 台北（台湾）
  • Year and Date: 2014-11-19 – 2014-11-21
• [Presentation] A Scheme of Test Pattern Generation to Reduce Over-testing of Path Delay Faults (2013)
  • Author(s): Kei Furumoto and Yuki Yoshikawa
  • Organizer: Proc. 3rd International Symposium on Technology for Sustainability (ISTS)
  • Place of Presentation: 香港（中国）
• [Presentation] A Binding Algorithm in High-Level Synthesis for Path Delay Testability (2013)
  • Author(s): Yuki Yoshikawa
  • Organizer: 18th Asia and South Pacific Design Automation Conference (ASP-DAC)
  • Place of Presentation: 国際会議場 パシフィコ横浜