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LSI design of secure and low-power adiabatic logic

Research Project

Project/Area Number 24760274
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeMulti-year Fund
Research Field Electron device/Electronic equipment
Research InstitutionGifu University

Principal Investigator

TAKAHASHI Yasuhiro  岐阜大学, 工学部, 准教授 (00402214)

Co-Investigator(Renkei-kenkyūsha) SEKINE Toshikazu  岐阜大学, 工学部, 准教授 (00108060)
YOKOYAMA Michio  山形大学, 大学院理工学研究科, 准教授 (40261573)
Research Collaborator SEKINE Toshikazu  
MONTEIRO Cancio  
Project Period (FY) 2012-04-01 – 2015-03-31
Project Status Completed (Fiscal Year 2014)
Budget Amount *help
¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000)
Fiscal Year 2014: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2013: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2012: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Keywords断熱的論理 / セキュア / AES
Outline of Final Research Achievements

This research proposes a new adiabatic logic which is named as Charge Sharing Symmetric Adiabatic logic (CSSAL). The comparison results of individual logics have shown that the proposed CSSAL circuit exhibits low and uniform peak supply current traces for all dual-input transistors, which performs its logic immunity for side-channel attacks. The designed Galois field multiplier and 8bit-Sbox LSIs have ultra low-power dissipation characteristics compared with the conventional LSIs. From the basis of the simulation and measurement results, we assures that the proposed logic has potential applicability for low-power and secure low frequency devices, such as in IC card, RFID tags, and/or wireless sensors.

Report

(4 results)
  • 2014 Annual Research Report   Final Research Report ( PDF )
  • 2013 Research-status Report
  • 2012 Research-status Report
  • Research Products

    (28 results)

All 2015 2014 2013 2012 Other

All Journal Article (6 results) (of which Peer Reviewed: 6 results) Presentation (20 results) (of which Invited: 1 results) Remarks (1 results) Patent(Industrial Property Rights) (1 results)

  • [Journal Article] Low-power secure S-Box circuit using CSSAL for AES hardware design2015

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Journal Title

      IET Circuits, Devices & Systems

      Volume: 9

    • Related Report
      2014 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Low power bit-parallel cellular multiplier implementation in secure dual-rail adiabatic logic2013

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Journal Title

      IACSIT International J. Modeling and Optimization

      Volume: 3 Pages: 329-332

    • DOI

      10.7763/ijmo.2013.v3.292

    • Related Report
      2013 Research-status Report
    • Peer Reviewed
  • [Journal Article] Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level2013

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Journal Title

      Microelectronics Journal,

      Volume: 44 Issue: 6 Pages: 496-503

    • DOI

      10.1016/j.mejo.2013.04.003

    • Related Report
      2013 Research-status Report
    • Peer Reviewed
  • [Journal Article] Low Power Supply Circuit Using Off-chip Resonant Circuit for Adiabatic Logic2013

    • Author(s)
      高橋康宏, 佐藤比佐夫
    • Journal Title

      IEEJ Transactions on Electronics, Information and Systems

      Volume: 133 Issue: 2 Pages: 220-225

    • DOI

      10.1541/ieejeiss.133.220

    • NAID

      10031142428

    • ISSN
      0385-4221, 1348-8155
    • Related Report
      2012 Research-status Report
    • Peer Reviewed
  • [Journal Article] The ramped-step voltage in adiabatic logic circuits: analysis of parameters to further reduce power dissipation2013

    • Author(s)
      N. A. Nayan, Y. Takahashi, and T. Sekine
    • Journal Title

      Research J. of Applied Sciences, Engineering and Technology

      Volume: 5 Pages: 114-117

    • Related Report
      2012 Research-status Report
    • Peer Reviewed
  • [Journal Article] LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier2012

    • Author(s)
      N. A. Nayan, Y. Takahashi, and T. Sekin
    • Journal Title

      Microelectronics Journal

      Volume: 43 Issue: 4 Pages: 244-249

    • DOI

      10.1016/j.mejo.2011.12.013

    • Related Report
      2012 Research-status Report
    • Peer Reviewed
  • [Presentation] Security evaluation of CSSAL countermeasure against side-channel attacks using frequency spectrum analysis2014

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Organizer
      電子情報通信学会EMCJ研究会
    • Place of Presentation
      浜松市
    • Year and Date
      2014-12-19
    • Related Report
      2014 Annual Research Report
  • [Presentation] Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation2014

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Organizer
      IEEE APCCAS 2014
    • Place of Presentation
      石垣市
    • Year and Date
      2014-11-17 – 2014-11-20
    • Related Report
      2014 Annual Research Report
  • [Presentation] Process variation verification of low-power secure CSSAL AES S-box2014

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Organizer
      IEEE MWSCAS 2014
    • Place of Presentation
      College Station, TX
    • Year and Date
      2014-08-03 – 2014-08-06
    • Related Report
      2014 Annual Research Report
  • [Presentation] An LSI implementation of a bit-parallel cellular multiplier over GF(2^4) using secure charge-sharing symmetric adiabatic logic2014

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Organizer
      IEEE ISCAS 2014
    • Place of Presentation
      Melbourne, Australia
    • Year and Date
      2014-06-01 – 2014-06-05
    • Related Report
      2014 Annual Research Report
  • [Presentation] Measurement of CSSAL Multiplier over GF(24) LSI Implemented in 0.18 µm CMOS Technology2014

    • Author(s)
      C. Monteiro, 高橋康宏, 関根敏和
    • Organizer
      2014年電子情報通信学会総合大会講演論文集
    • Place of Presentation
      新潟市
    • Related Report
      2013 Research-status Report
  • [Presentation] LSI iplementation of a secure low-power CSSAL cellular multiplier2013

    • Author(s)
      C. Monteiro, 高橋康宏, 関根敏和
    • Organizer
      電子情報通信学会CAS研究会
    • Place of Presentation
      岐阜市
    • Related Report
      2013 Research-status Report
  • [Presentation] 負荷容量均一化対称構造断熱的論理回路CSSAL ~論理回路設計と暗号回路設計の事例~2013

    • Author(s)
      高橋康宏, C. Monteiro, 関根敏和
    • Organizer
      電子情報通信学会CAS研究会
    • Place of Presentation
      岐阜市
    • Related Report
      2013 Research-status Report
    • Invited
  • [Presentation] LSI implementation of a bit-parallel cellular multiplier over GF(24) using charge-sharing symmetric adiabatic logic2013

    • Author(s)
      C. Monteiro, 高橋康宏, 関根敏和
    • Organizer
      2013年電子情報通信学会ソサイエティ大会
    • Place of Presentation
      福岡市
    • Related Report
      2013 Research-status Report
  • [Presentation] Low power secure CSSAL bit-parallel multiplier over GF(2^4) in 0.18 um CMOS technology2013

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Organizer
      IEEE ECCTD 2013
    • Place of Presentation
      Dresden, Germany
    • Related Report
      2013 Research-status Report
  • [Presentation] Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks2013

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Organizer
      IEEE TSP 2013
    • Place of Presentation
      Roma, Italy
    • Related Report
      2013 Research-status Report
  • [Presentation] Low power secure AES S-box using adiabatic logic circuit2013

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Organizer
      IEEE FTFC 2013
    • Place of Presentation
      Paris, France
    • Related Report
      2013 Research-status Report
  • [Presentation] DPA resistance of charge-sharing symmetric adiabatic logic2013

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Organizer
      IEEE ISCAS 2013
    • Place of Presentation
      Beijing, China
    • Related Report
      2013 Research-status Report
  • [Presentation] Low power bit-parallel multiplier over GF(2^4) using CSSAL for cryptographic hardware implementation2013

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Organizer
      IEEE Coolchips XVI,
    • Place of Presentation
      横浜市
    • Related Report
      2013 Research-status Report
  • [Presentation] Low power CSSAL bit-parallel multiplier over GF(2^4) in 0.18 um CMOS technology2013

    • Author(s)
      C. Monteiro, 高橋康宏, 関根敏和
    • Organizer
      電子情報通信学会EMCJ研究会
    • Place of Presentation
      岡山市
    • Related Report
      2013 Research-status Report
  • [Presentation] Secure charge-sharing symmetric adiabatic logic implementation in AES S-Box architecture for smart card2013

    • Author(s)
      C. Monteiro, Y. Takahashi, and T. Sekine
    • Organizer
      IEEE ICEIC 2013
    • Place of Presentation
      Bali, Indonesia
    • Related Report
      2012 Research-status Report
  • [Presentation] Low power CSSAL bit-parallel multiplier over GF(2^4) in 0.18 µm CMOS technology2012

    • Author(s)
      C. Monteiro, 高橋康宏, 関根敏和
    • Organizer
      電子情報通信学会EMCJ研究会
    • Place of Presentation
      岐阜市
    • Related Report
      2012 Research-status Report
  • [Presentation] Power-saving analysis of adiabatic logic in subthreshold region2012

    • Author(s)
      Y. Takahashi, T. Sekine, N. A. Nayan, and M. Yokoyama
    • Organizer
      IEEE ISPACS 2012
    • Place of Presentation
      Tamsui, Taiwan
    • Related Report
      2012 Research-status Report
  • [Presentation] Investigation study of inner-cell bit-parallel multiplier over GF(2m) using secure adiabatic logic style2012

    • Author(s)
      C. Monteiro, 高橋康宏, 関根敏和
    • Organizer
      2012年電子情報通信学会ソサエティ大会
    • Place of Presentation
      富山市
    • Related Report
      2012 Research-status Report
  • [Presentation] サブスレッショルド断熱的論理回路の性能解析と省電力効果2012

    • Author(s)
      高橋康宏, 関根敏和, 横山道央
    • Organizer
      2012年電子情報通信学会ソサエティ大会
    • Place of Presentation
      富山市
    • Related Report
      2012 Research-status Report
  • [Presentation] A comparison of cellular multiplier cell for finite field GF(2^m) using secure adiabatic logics2012

    • Author(s)
      C. Monteiro, 高橋康宏, 関根敏和
    • Organizer
      電気学会電子回路研究会
    • Place of Presentation
      米沢市
    • Related Report
      2012 Research-status Report
  • [Remarks] 高橋康宏 (Yasuhiro TAKAHASHI)

    • URL

      http://www1.gifu-u.ac.jp/~yasut/

    • Related Report
      2013 Research-status Report
  • [Patent(Industrial Property Rights)] 差動論理によりサイドチャネル攻撃から保護される暗号回路2012

    • Inventor(s)
      高橋康宏, モンテイロカンシオ, 関根敏和
    • Industrial Property Rights Holder
      高橋康宏, モンテイロカンシオ, 関根敏和
    • Industrial Property Rights Type
      特許
    • Industrial Property Number
      2012-274909
    • Filing Date
      2012-12-19
    • Related Report
      2012 Research-status Report

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Published: 2013-05-31   Modified: 2019-07-29  

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