A Fast Settling ADPLL for Periodically Wake-Up Systems
| Project/Area Number |
24760279
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Kobe University |
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Principal Investigator |
IZUMI Shintaro 神戸大学, 自然科学系先端融合研究環重点研究部, 助教 (60621646)
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| Project Period (FY) |
2012-04-01 – 2014-03-31
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| Project Status |
Completed (Fiscal Year 2013)
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| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2013: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2012: ¥3,120,000 (Direct Cost: ¥2,400,000、Indirect Cost: ¥720,000)
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| Keywords | 位相同期回路 / 間欠動作 / 温度補償 / 時間デジタル変換 / 周波数ホッピング |
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| Research Abstract |
In this research, a temperature compensation technique for a digitally controlled oscillator (DCO) using least means square (LMS) filtering was proposed. The proposed scheme contributes to reduction of the start-up settling time of all-digital phase-locked loop (ADPLL). The proposed method estimates the temperature using the output frequency of DCO because it is affected by temperature fluctuation. These characteristics are confirmed using measurement results of the test chip, which is fabricated in 65-nm CMOS process.
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Report
(3 results)
Research Products
(6 results)
