A Universal Memory Architecture Based on Device-Architecture Co-Design
| Project/Area Number |
25280012
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Partial Multi-year Fund |
|---|
| Section | 一般 |
|---|
| Research Field |
Computer system
|
|---|
| Research Institution | Tohoku University |
|---|
Principal Investigator |
Kobayashi Hiroaki 東北大学, サイバーサイエンスセンター, 教授 (40205480)
|
|---|
| Co-Investigator(Renkei-kenkyūsha) |
TAKIZAWA HIROYUKI 東北大学, 大学院情報科学研究科, 准教授 (70323996)
EGAWA RYUSUKE 東北大学, サイバーサイエンスセンター, 准教授 (80374990)
|
|---|
| Project Period (FY) |
2013-04-01 – 2016-03-31
|
| Project Status |
Completed (Fiscal Year 2015)
|
| Budget Amount *help |
¥17,810,000 (Direct Cost: ¥13,700,000、Indirect Cost: ¥4,110,000)
Fiscal Year 2015: ¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000)
Fiscal Year 2014: ¥6,240,000 (Direct Cost: ¥4,800,000、Indirect Cost: ¥1,440,000)
Fiscal Year 2013: ¥5,070,000 (Direct Cost: ¥3,900,000、Indirect Cost: ¥1,170,000)
|
|---|
| Keywords | メモリシステム / キャッシュデータ管理ポリシー / メモリ階層管理 / キャッシュメモリ / 低消費電力制御 / 高バンド幅キャッシュ / 3次元実装 / 2.5次元実装 / チェックポイントリスタート機能 |
|---|
| Outline of Final Research Achievements |
The objective of this study is to establish a smart memory subsystem architecture that can consider memory access behaviors of applications and effectively manage data in the memory hierarchy in terms of performance and power efficiency. In particular, we have developed 1) a low-power/high-bandwidth cache architecture, 2) a cache management policy with an on-line evaluation of the memory request behavior of an application for reducing its working set in the memory hierarchy, 3) a cache partitioning mechanism to protect performance-sensitive shared data for chip multicore processors, 4)a memory address mapping mechanism with the performance/performance optimization by using an online-estimation of memory access behavior.
|
Report
(4 results)
Research Products
(20 results)
