| Project/Area Number |
25280014
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Partial Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Kyoto University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
土谷 亮 京都大学, 情報学研究科, 助教 (20432411)
石原 亨 京都大学, 情報学研究科, 准教授 (30323471)
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| Co-Investigator(Renkei-kenkyūsha) |
NISHIZAWA Sinichi 埼玉大学, 大学院理工学研究科, 助教 (40757522)
Mahfuzul Islam A. K. M. 東京大学, 生産技術研究所, 助教 (80762195)
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| Project Period (FY) |
2013-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥18,200,000 (Direct Cost: ¥14,000,000、Indirect Cost: ¥4,200,000)
Fiscal Year 2015: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2014: ¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2013: ¥8,840,000 (Direct Cost: ¥6,800,000、Indirect Cost: ¥2,040,000)
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| Keywords | システムオンチップ / 集積回路 / 低消費電力化 / 製造容易化 / 組込みシステム / ディペンダブルシステム / 組込システム |
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| Outline of Final Research Achievements |
Under low voltage operation, variability of circuit performance increases due to process variations, which may result in functional failure. In order to maintain robust operation under low supply voltage close to the threshold voltage of transistors, an on-chip monitor circuit for estimating process variations and a body-bias generator for compensating the estimated process variations have been developed. Analytical stability modeling for CMOS latches, which are known to be susceptible to process variations, has been developed and design guidelines for variation-tolerant latches have been derived. With those techniques, a circuit with stable operation under low supply voltage down to the threshold voltage of transistors can be realized.
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