Research on Built-in Self-Test to Enhance LSI Reliability through its Lifecycle

• Project/Area Number: 25280015
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Partial Multi-year Fund
• Section: 一般
• Research Field: Computer system
• Research Institution: Nara Institute of Science and Technology
• Principal Investigator: Inoue Michiko 奈良先端科学技術大学院大学, 情報科学研究科, 教授 (30273840)
• Co-Investigator(Kenkyū-buntansha): YONEDA Tomokazu 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (20359871) ; YAMATO Yuta 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (20707244)
• Project Period (FY): 2013-04-01 – 2016-03-31
• Project Status: Completed (Fiscal Year 2015)
• Budget Amount: ¥10,140,000 (Direct Cost: ¥7,800,000、Indirect Cost: ¥2,340,000); Fiscal Year 2015: ¥2,730,000 (Direct Cost: ¥2,100,000、Indirect Cost: ¥630,000); Fiscal Year 2014: ¥2,730,000 (Direct Cost: ¥2,100,000、Indirect Cost: ¥630,000); Fiscal Year 2013: ¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
• Keywords: LSI信頼性 / 組み込み自己テスト / IRドロップ / 組み込みメモリ / 計算機システム / ディペンダブル・コンピューティング / ディペダブル・コンピューティング

Outline of Final Research Achievements

We have conducted a research on LSI reliability through its lifecycle. Our achievement includes 1) reduction of test data volume and test application time of LSI Built-in Self-Test (BIST) so that LSI BIST can be applicable in field as well as at manufacturing test, 2) analysis of IR-drop and delay defects to improve test quality, and 3) embedded memory architecture to enhance reliability in field with combination of ECC and self-test and repair techniques.

Research Products

• [Int'l Joint Research] University of Stuttgart(Germany)
• [Presentation] Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC (2016)
  • Author(s): Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue
  • Organizer: the 21st IEEE European Test Symposium
  • Place of Presentation: Amsterdam, The Netherlands
  • Year and Date: 2016-05-24
  • Int'l Joint Research
• [Presentation] 重み付きランダムパターンとリシードを組み合わせた組込み自己テスト手法 (2016)
  • Author(s): 里中 沙矢香, 米田 友和, 大和 勇太, 井上 美智子
  • Organizer: 電子情報通信学会ディペンダブルコンピューティング研究会
  • Place of Presentation: 機械振興会館（東京都港区）
  • Year and Date: 2016-02-17
• [Presentation] ゼロ遅延論理シミュレーションに基づく遅延故障インジェクション環境 (2016)
  • Author(s): 川崎 真司, 米田 友和, 大和 勇太, 井上 美智子
  • Organizer: 電子情報通信学会ディペンダブルコンピューティング研究会
  • Place of Presentation: 機械振興会館（東京都港区）
  • Year and Date: 2016-02-17
• [Presentation] メモリの隣接パタン依存故障テストに対するバックグラウンド列の生成 (2015)
  • Author(s): 上岡真也, 米田友和, 大和勇太, 井上美智子
  • Organizer: 電子情報通信学会ディペンダブルコンピューティング研究会
  • Place of Presentation: 福江文化会館（長崎県五島市）
  • Year and Date: 2015-12-01
• [Presentation] An ECC-Based memory architecture with online self-repair capabilities for reliability enhancement (2015)
  • Author(s): Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue
  • Organizer: IEEE European Test Symposium
  • Place of Presentation: Cluj-Napoca, Romania
  • Year and Date: 2015-05-25 – 2015-05-29
• [Presentation] An ECC-Based memory architecture with online self-repair capabilities for reliability enhancement (2015)
  • Author(s): Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue
  • Organizer: the 20th IEEE European Test Symposium
  • Place of Presentation: Cluj-Napoca, Romania
  • Year and Date: 2015-05-25
  • Int'l Joint Research
• [Presentation] Reliability of ECC-based memory architectures with online self-repair capabilities (2014)
  • Author(s): Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue
  • Organizer: 電子情報通信学会ディペンダブルコンピューティング研究会
  • Place of Presentation: 高岡テクノドーム（富山県高岡市）
  • Year and Date: 2014-12-19
• [Presentation] An online repair strategy and reliability for ECC-Based memory architectures (2014)
  • Author(s): Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato and Michiko Inoue
  • Organizer: IEEE Workshop on RTL and High Level Testing
  • Place of Presentation: Hangzhou, China
  • Year and Date: 2014-11-19 – 2014-11-20
• [Presentation] Parallel path delay fault simulation for multi/many-core processors with SIMD units (2014)
  • Author(s): Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue
  • Organizer: IEEE Asian Test Symposium
  • Place of Presentation: Hangzhou, China
  • Year and Date: 2014-11-16 – 2014-11-19
• [Presentation] Memory block based scan-BIST architecture for application-dependent FPGA testing (2014)
  • Author(s): Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue
  • Organizer: ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
  • Place of Presentation: Monterey, California, USA
• [Presentation] Efficient scan-based BIST architecture for application-dependent FPGA test (2013)
  • Author(s): Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue
  • Organizer: The Forteenth Workshop on RTL and High Level Testing
  • Place of Presentation: 台湾・宜蘭
• [Presentation] FPGA向けアプリケーション依存テストのための効率的なスキャンBISTアーキテクチャ (2013)
  • Author(s): 伊藤 渓太, 米田 友和, 大和 勇太, 畠山 一実, 井上 美智子
  • Organizer: 電子情報通信学会ディペンダブルコンピューティング研究会
  • Place of Presentation: 石川県七尾市