| Budget Amount *help |
¥18,200,000 (Direct Cost: ¥14,000,000、Indirect Cost: ¥4,200,000)
Fiscal Year 2015: ¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2014: ¥5,850,000 (Direct Cost: ¥4,500,000、Indirect Cost: ¥1,350,000)
Fiscal Year 2013: ¥7,540,000 (Direct Cost: ¥5,800,000、Indirect Cost: ¥1,740,000)
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| Outline of Final Research Achievements |
In this research, we first propose an abstract LSI model, where functional units, registers and control units are packed into one functional block and hence interconnection delays can be ignored in it. Based on these functional blocks, we secondly propose a high-level synthesis algorithm which integrates behavioral synthesis and physical synthesis into a single synthesis flow. Experimental results demonstrate that our proposed synthesis algorithm successfully reduces the energy of a synthesized LSI chip by a maximum of 50%.
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