| Budget Amount *help |
¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2016: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2015: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2014: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2013: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Outline of Final Research Achievements |
The increase of transistor count allows us to implement multicore-CPU and GPU combined heterogeneous architecture on a single chip. We have designed a source-level loop parallelization system framework for the heterogeneous architecture. Following the designed framework, we have developed a path and data-dependency profiling tool using Valgrind. By applying the system to benchmark programs, we have clarified the characteristics of each loop of the programs and showed that we can utilize the profiled results to determine the parallelizing scheme on heterogeneous architecture
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