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A processor core for many-core with fine grained PSU and ALU cascading control

Research Project

Project/Area Number 25330060
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Computer system
Research InstitutionNagoya University

Principal Investigator

Shimada Hajime  名古屋大学, 情報基盤センター, 准教授 (60377851)

Co-Investigator(Kenkyū-buntansha) KOBAYASHI Ryotaro  豊橋技術科学大学, 工学(系)研究科(研究院), 講師 (40324454)
Project Period (FY) 2013-04-01 – 2016-03-31
Project Status Completed (Fiscal Year 2015)
Budget Amount *help
¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2015: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Fiscal Year 2014: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Keywordsプロセッサアーキテクチャ / 低電力アーキテクチャ / 高回路面積効率アーキテクチャ
Outline of Final Research Achievements

To propose energy and area efficient processor, we explored the processor with fine grained ALU cascading (ALU-C) and pipeline stage unification (PSU). The result shows that 3-way in-order processor with ALU-C achieves close performance to 2-way out-of-order processor without PSU. Similarlly, 4-way in-order processor with ALU-C achieves close performance to 3-way out-of-order processor with less resources for out-of-order. Thus, we can achieve energy and area efficient processor only with ALU-C.

Report

(4 results)
  • 2015 Annual Research Report   Final Research Report ( PDF )
  • 2014 Research-status Report
  • 2013 Research-status Report
  • Research Products

    (11 results)

All 2016 2015 2014 2013 Other

All Journal Article (2 results) (of which Peer Reviewed: 2 results,  Acknowledgement Compliant: 2 results) Presentation (7 results) Remarks (2 results)

  • [Journal Article] Energy Reduction of BTB by focusing on Number of Branches per Cache Line2016

    • Author(s)
      Ryotaro Kobayashi, Kaoru Saito, and Hajime Shimada
    • Journal Title

      IPSJ Journal of Information Processing

      Volume: Vol. 24, No. 3

    • NAID

      110010021441

    • Related Report
      2015 Annual Research Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Journal Article] BTB Energy Reduction by Focusing on Useless Accesses2015

    • Author(s)
      Yoshio Shimomura, Hiroki Yamamoto, Hayato Usui, Ryotaro Kobayashi, and Hajime Shimada
    • Journal Title

      IEICE Transactions on Electronics

      Volume: Vol. E98-C, No. 7 Pages: 569-579

    • NAID

      130005086131

    • Related Report
      2015 Annual Research Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Presentation] パス限定ALUカスケーディングのための命令並び替えの設計と評価2016

    • Author(s)
      鈴木杏理, 嶋田創, 小林良太郎
    • Organizer
      情報処理学会全国大会, 6G-06
    • Place of Presentation
      神奈川県横浜市
    • Year and Date
      2016-03-10
    • Related Report
      2015 Annual Research Report
  • [Presentation] アプリケーション主導のリンク速度調整による有線イーサネット消費電力量削減2015

    • Author(s)
      吉田慎吾, 嶋田創, 山口由紀子, 高倉弘喜
    • Organizer
      情報処理学会研究報告, Vol. 2015-IOT-29, No. 7, pp. 1-8,
    • Place of Presentation
      大分県別府市
    • Year and Date
      2015-05-21
    • Related Report
      2015 Annual Research Report
  • [Presentation] 細粒度なヘテロジニアスクラスタコアによる消費電力削減の提案2015

    • Author(s)
      金子郁未, 小林良太郎, 嶋田創
    • Organizer
      情報処理学会 第77回 全国大会予稿集, 4J-06
    • Place of Presentation
      京都府京都市
    • Year and Date
      2015-03-17 – 2015-03-19
    • Related Report
      2014 Research-status Report
  • [Presentation] ALUカスケーディングと3-wayインオーダ実行を併用したメニーコア向けプロセッサ・コアの検討2014

    • Author(s)
      嶋田創, 小林良太郎
    • Organizer
      電子情報通信学会技術報告, Vol. 114, No. 242, CPSY2014-53, pp. 37-42
    • Place of Presentation
      千葉県千葉市
    • Year and Date
      2014-10-10
    • Related Report
      2014 Research-status Report
  • [Presentation] Instruction Steering Method by Utilizing Redundancy of Data Bit Width2014

    • Author(s)
      I. Kaneko, S. Kawai, R. Kobayashi, and H. Shimada
    • Organizer
      The 17th International Symposium on Low-Power and High-Speed Chips (COOLChips XVII), Poster 2
    • Place of Presentation
      Yokohama / Japan
    • Year and Date
      2014-04-14 – 2014-04-16
    • Related Report
      2014 Research-status Report
  • [Presentation] ALU Cascading Based on Different Execution Latencies of Each Instruction (Poster)2013

    • Author(s)
      Hiroki Yamamoto, Kazuki Sekikawa, Ryotaro Kobayashi, Hajime Shimada
    • Organizer
      The 16th International Symposium on Low-Power and High-Speed Chips (COOLChips XVI)
    • Place of Presentation
      Yokohama / Japan
    • Related Report
      2013 Research-status Report
  • [Presentation] レジスタ値の部分更新による低消費エネルギー指向ヘテロジニアス・クラスタ型プロセッサ2013

    • Author(s)
      川合翔麻, 小林良太郎, 嶋田創
    • Organizer
      電子情報通信学会技術報告, CPSY2013-39
    • Place of Presentation
      広島県東広島市
    • Related Report
      2013 Research-status Report
  • [Remarks] 計算機アーキテクチャ関係の研究

    • URL

      http://www.net.itc.nagoya-u.ac.jp/member/shimada/researches/architecture.html

    • Related Report
      2015 Annual Research Report
  • [Remarks] 計算機アーキテクチャ関係の研究

    • URL

      http://www.net.itc.nagoya-u.ac.jp/~shimada/researches/architecture.html

    • Related Report
      2013 Research-status Report

URL: 

Published: 2014-07-25   Modified: 2019-07-29  

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