Study on test and diagnosis for defects on vias in 3D-LSIs
| Project/Area Number |
25330062
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Ehime University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
TAKAHASHI HIROSHI 愛媛大学, 大学院理工学研究科, 教授 (80226878)
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| Project Period (FY) |
2013-04-01 – 2016-03-31
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| Project Status |
Completed (Fiscal Year 2015)
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| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2015: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2014: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2013: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | LSI / 故障診断 / 遅延故障 / 3次元LSI / LSIのテスト / LSIの故障診断 |
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| Outline of Final Research Achievements |
When physical defects occur at vias in 3D-LSIs, propagation of signals will delay. In this research we develop diagnosis methods for delay faults. Targets are delay faults on gate signal lines and clock lines which have various amounts of delay. Also we consider hazard signals which change values temporarily. The effectiveness of the developed methods has been confirmed in the experiments for benchmark circuits.
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Report
(4 results)
Research Products
(11 results)
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[Journal Article] Message from the Editor-in-Chief2016
Author(s)
Y. Higami, S. Wang, H. Takahashi, S. Kobayashi and K. K. Saluja
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Journal Title
IPSJ Transactions on System LSI Design Methodology
Volume: 9
Issue: 0
Pages: 1-1
DOI
NAID
ISSN
1882-6687
Related Report
Peer Reviewed / Int'l Joint Research / Acknowledgement Compliant
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