| Budget Amount *help |
¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2015: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2014: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2013: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Outline of Final Research Achievements |
To drive forward the green computing technology, which enables an efficient power performance ratio, it is necessary to achieve both architectural power saving techniques and highly efficient power feed control. In this work, assuming FPGA accelerators tightly coupled with multiple power supply unit modules, characteristics models of an FPGA accelerator were derived and shown to be useful for power performance optimisation. In addition, FPGA-based power feed control techniques were also proposed and the effectiveness was demonstrated by simulation analysis and empirical experiments.
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