Development of a validity check program for real time parallel systems using timed CSP
Project/Area Number |
25330087
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Research Category |
Grant-in-Aid for Scientific Research (C)
|
Allocation Type | Multi-year Fund |
Section | 一般 |
Research Field |
Software
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Research Institution | Tokyo Metropolitan University |
Principal Investigator |
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Project Period (FY) |
2013-04-01 – 2016-03-31
|
Project Status |
Completed (Fiscal Year 2015)
|
Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2015: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2014: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2013: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
|
Keywords | 並列処理 / 形式手法 / CSP理論 / 失敗・発散検査 / 並列システム記述理論 / 形式理論 / timed-CSP / FDR(失敗-発散-詳細化解析) / FDR(失敗-発散-詳細化)解析 / 国際情報交換(英国、シンガポール) / 国際情報交換(英国、米国) |
Outline of Final Research Achievements |
The study is concerned with a validity check program for a parallel processing system. If some units are run in parallel, the system will be dead-locked with unexpected sequence failures. We have a tool to find them hidden in a system at the system design level. Our study has tried to refine the validity checker to discover invalidities caused by timing conflict beside simple event sequence. We have confirmed that some of timing invalidities possibly hidden in a system could be found with this newly refined checker.
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Report
(4 results)
Research Products
(5 results)