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Development of Host-Based IPS Processor Using Delay Adjustment Method by Routing and Optimization of Detection Circuits

Research Project

Project/Area Number 25330149
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Research Field Information security
Research InstitutionHirosaki University

Principal Investigator

Sato Tomoaki  弘前大学, 総合情報処理センター, 准教授 (00336992)

Project Period (FY) 2013-04-01 – 2017-03-31
Project Status Completed (Fiscal Year 2016)
Budget Amount *help
¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2015: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2014: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2013: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
KeywordsIDS / IPS / FPGA / RTL / ウェーブパイプライン / 不正アクセス / 不正アクセス防御システム / 再構成可能なハードウエア / パケット収集 / モバイルコンピューティング / タイミング調整 / コネクションスイッチ / 再構成可能なハードウェア
Outline of Final Research Achievements

Unauthorized access and computer viruses cause problems with information leakage and tampering. Actually, a targeted attack made leakage of personal information in Japan Pension Service. In order to avoid unauthorized access and computer viruses, Intrusion Detection Systems (IDSs) or Intrusion Prevention Systems (IPSs) should be used. In this study, it is clarified that a fine-tuning method for wave-pipelining can be realized on reconfigurable hardware for the purpose of addressing these problems with a technical approach in mobile devices. In addition, the optimization of the detection circuit was realized by ASIC-FPGA co-design.

Report

(5 results)
  • 2016 Annual Research Report   Final Research Report ( PDF )
  • 2015 Research-status Report
  • 2014 Research-status Report
  • 2013 Research-status Report
  • Research Products

    (19 results)

All 2017 2016 2015 2014 2013 Other

All Int'l Joint Research (2 results) Journal Article (14 results) (of which Int'l Joint Research: 8 results,  Peer Reviewed: 14 results,  Open Access: 2 results,  Acknowledgement Compliant: 12 results) Presentation (3 results) (of which Int'l Joint Research: 2 results)

  • [Int'l Joint Research] KMITL(Thailand)

    • Related Report
      2016 Annual Research Report
  • [Int'l Joint Research] KMITL(Thailand)

    • Related Report
      2015 Research-status Report
  • [Journal Article] RCA on FPGAs Designed by the RTL Design Methodology and Wave-Pipelined Operation2017

    • Author(s)
      T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi
    • Journal Title

      ECTI Transactions on Computer and Information Technology

      Volume: 11 Pages: 10-19

    • Related Report
      2016 Annual Research Report
    • Peer Reviewed / Open Access / Int'l Joint Research / Acknowledgement Compliant
  • [Journal Article] Throughput of a Firewall Unit on FPGAs developed by the RTL Design Methodology2017

    • Author(s)
      T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi
    • Journal Title

      Proc. of iEECON 2017

      Volume: 2 Pages: 423-426

    • Related Report
      2016 Annual Research Report
    • Peer Reviewed / Int'l Joint Research / Acknowledgement Compliant
  • [Journal Article] An FPGA Architecture for ASIC-FPGA Co-Design to Streamline Processing of IDSs2016

    • Author(s)
      T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi
    • Journal Title

      Proc. of CTS 2016

      Volume: - Pages: 53-58

    • DOI

      10.1109/cts.2016.0079

    • Related Report
      2016 Annual Research Report
    • Peer Reviewed / Int'l Joint Research / Acknowledgement Compliant
  • [Journal Article] Designing a Firewall Unit on the FPGA Composed of Selectors2016

    • Author(s)
      T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi,
    • Journal Title

      Proc. of SISA 21016

      Volume: - Pages: 53-58

    • Related Report
      2016 Annual Research Report
    • Peer Reviewed / Int'l Joint Research / Acknowledgement Compliant
  • [Journal Article] A Connection Block Implemented in the RTL Design for Delay Time Equalization of Wave-Pipelining2016

    • Author(s)
      T. Sato, S. Chivapreecha and P. Moungnoul
    • Journal Title

      Journal on Systemics, Cybernetics and Informatics

      Volume: 14 Pages: 49-54

    • Related Report
      2015 Research-status Report
    • Peer Reviewed / Open Access / Int'l Joint Research / Acknowledgement Compliant
  • [Journal Article] Fine-Tuning of Wave-Pipelines on FPGAs Developed by the RTL Design2015

    • Author(s)
      T. Sato, S. Chivapreecha and P. Moungnoul
    • Journal Title

      Proc. of ECTI-CON 21015

      Volume: 1 Pages: 1-6

    • DOI

      10.1109/ecticon.2015.7207067

    • Related Report
      2015 Research-status Report
    • Peer Reviewed / Int'l Joint Research / Acknowledgement Compliant
  • [Journal Article] The Potential of Routes Configured with the Switch Matrix by RTL2015

    • Author(s)
      T. Sato, S. Chivapreecha and P. Moungnoul
    • Journal Title

      Applied Mechanics and Materials Journal

      Volume: 781 Pages: 189-192

    • DOI

      10.4028/www.scientific.net/amm.781.189

    • Related Report
      2015 Research-status Report
    • Peer Reviewed / Int'l Joint Research / Acknowledgement Compliant
  • [Journal Article] Proposal of the security log collection method of public Wi-Fi services on private IPv4 address spaces utilizing Raspberry Pi2015

    • Author(s)
      T. Sato, S. Chivapreecha and P. Moungnoul and K. Higuchi
    • Journal Title

      Proc. of ICESIT 2015

      Volume: 1 Pages: 6-7

    • Related Report
      2015 Research-status Report
    • Peer Reviewed / Int'l Joint Research / Acknowledgement Compliant
  • [Journal Article] Evaluation of Logic Blocks for Reconfigurable Wave-Pipelined Circuits with 45nm CMOS Technology2014

    • Author(s)
      Tomoaki Sato, Sorawat Chivapreecha, Phichet Moungnoul
    • Journal Title

      Proc. of ITC-CSCC2014

      Volume: 0 Pages: 464-465

    • Related Report
      2014 Research-status Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Journal Article] Wiring Control by RTL Design for Reconfigurable Wave-Pipelined Circuits2014

    • Author(s)
      T. Sato, S. Chivapreecha and P. Moungnoul
    • Journal Title

      Proc. of APSIPA ASC 2014

      Volume: 0

    • Related Report
      2014 Research-status Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Journal Article] Design and Analysis of Crossbar Switch Circuits for Reconfigurable Wave-Pipelined Circuits2014

    • Author(s)
      T. Sato, S. Chivapreecha and P. Moungnoul
    • Journal Title

      Proc. of CreTech 2014

      Volume: 0 Pages: 12-15

    • Related Report
      2014 Research-status Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Journal Article] A Crossbar Switch Circuit Design for Reconfigurable Wave-Pipelined Circuits2014

    • Author(s)
      Tomoaki Sato, Sorawat Chivapreecha, Phichet Moungnoul
    • Journal Title

      Proc. of WMSCI 2014

      Volume: II Pages: 200-205

    • Related Report
      2014 Research-status Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Journal Article] Performance Estimates of an Embedded CPU for High-Speed Packet Processing2014

    • Author(s)
      Tomoaki Sato, Sorawat Chivapreecha, Phichet Moungnoul and Kohji Higuchi
    • Journal Title

      Proc. of ECTI-CON 2014

      Volume: 1 Pages: 1-5

    • Related Report
      2013 Research-status Report
    • Peer Reviewed
  • [Journal Article] A Logic Block for Wave-Pipelining2013

    • Author(s)
      Tomoaki Sato, Sorawat Chivapreecha, Phichet Moungnoul
    • Journal Title

      Proc. of IMETI 2013

      Volume: 1 Pages: 130-134

    • Related Report
      2013 Research-status Report
    • Peer Reviewed
  • [Presentation] RCA on FPGAs Designed by the RTL Design Methodology and Wave-Pipelined Operation2016

    • Author(s)
      T. Sato, S. Chivapreecha, P. Moungnoul and K. Higuchi,
    • Organizer
      ECTI-CON 2016
    • Place of Presentation
      Chiang Mai, Thailand
    • Year and Date
      2016-06-28
    • Related Report
      2016 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Connection Block Implemented in the RTL Design for Delay Time Equalization of Wave-Pipelining2015

    • Author(s)
      T. Sato, S. Chivapreecha and P. Moungnoul
    • Organizer
      The 19th World Multi-Conference on Systemics, Cybernetics and Informatics
    • Place of Presentation
      Florida, USA
    • Year and Date
      2015-07-12
    • Related Report
      2015 Research-status Report
    • Int'l Joint Research
  • [Presentation] The Potential of Routes Configured with the Switch Matrix by RTL2015

    • Author(s)
      Tomoaki Sato
    • Organizer
      The 2015 International Electrical Engineering Congress
    • Place of Presentation
      Phuket, Thailand
    • Year and Date
      2015-03-19
    • Related Report
      2014 Research-status Report

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Published: 2014-07-25   Modified: 2019-07-29  

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