Self-Aligned Four-Terminal Low-Temperature Poly-Si TFTs on Glass Substrate
| Project/Area Number |
25420339
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tohoku Gakuin University |
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Principal Investigator |
Hara Akito 東北学院大学, 工学部, 教授 (20417398)
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| Co-Investigator(Renkei-kenkyūsha) |
Kitahara Kuninori 島根大学, 総合理工学部, 教授 (60304250)
Sugawara Fumihiko 東北学院大学, 工学部, 准教授 (70171139)
Suzuki Hitoshi 東北学院大学, 工学部, 准教授 (70351319)
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| Project Period (FY) |
2013-04-01 – 2016-03-31
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| Project Status |
Completed (Fiscal Year 2015)
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| Budget Amount *help |
¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2015: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2014: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2013: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | 薄膜トランジスタ / poly-Si / poly-Ge / ダブルゲート / 四端子 / ガラス / poly-Si TFT / 低温プロセス / poly-Ge TFT / 多結晶シリコン / 4端子 / ４端子 / 自己整合 |
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| Outline of Final Research Achievements |
In the current study, the fabrication of low temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistor (TFT) was achieved using continuous-wave laser lateral crystallization (CLC). In order to control the Vth of the LT poly-Si TFTs, we fabricated self-aligned four-terminal (4T) LT poly-Si TFTs using high-quality CLC poly-Si film. The self-aligned 4T CLC LT poly-Si TFTs showed excellent Vth controllability. The variation of the Vth of the drive gate TFT, with respect to small variation in the control gate voltage, was found to closely match the theoretically predicted values of the top and bottom gate drives for both n- and p-ch TFTs. By exploiting the high controllability of the 4T TFTs, an E/D inverter was fabricated and successfully operated at 2.0 V.
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Report
(4 results)
Research Products
(55 results)
