Efficient Subtract-Multiply Operation Circuit Design Using Selector Logics
| Project/Area Number |
25540021
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | Waseda University |
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Principal Investigator |
TOGAWA NOZOMU 早稲田大学, 理工学術院, 教授 (30298161)
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| Project Period (FY) |
2013-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2014: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Fiscal Year 2013: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Keywords | セレクタ演算 / 差積演算 / 画像処理 |
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| Outline of Final Research Achievements |
A subtract-multiply operation, (a-b)*c, is a basic and important operation in image processing but it requires much computation time since we first calculate t=(a-b) and, after that, we calculate t*c. In this report, we first show that the subtract-multiply operation can be effectively implemented by “selectors.” After that, we pick up bi-linear interpolation and apply the selector-logics to it. Selector logics can reduce the carry-propagations and then we can realize area-efficient and fast dedicated circuits. We have implemented our proposed bi-linear interpolation circuit in several ways and evaluated each of them.
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Report
(3 results)
Research Products
(9 results)
