| Project/Area Number |
25540024
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Software
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| Research Institution | Hiroshima University |
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Principal Investigator |
Nakano Koji 広島大学, 工学(系)研究科(研究院), 教授 (30281075)
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| Co-Investigator(Kenkyū-buntansha) |
Ito Yasuaki 広島大学, 大学院工学研究院, 准教授 (40397964)
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| Project Period (FY) |
2013-04-01 – 2016-03-31
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| Project Status |
Completed (Fiscal Year 2015)
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| Budget Amount *help |
¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2015: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2014: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2013: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Keywords | FGPA / ハードウェアアルゴリズム / 開発環境 / FPGA / ハードウェアアルゴリズ |
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| Outline of Final Research Achievements |
The main purpose of this work is to develop a GPFPGA(General Purpose computing using Field Programmable Gate Arrays) method and to show capability of general purpose computing using FPGAs. For this purpose, we have developed FDFM approach (Few DSP slices Few Memory block approach), which implement a special-purpose processor using few DSP slices and Few Memory blocks in an FPGA. By this approach, we have accelerated the computation as follows: (1) real-time line detection in an image using Hough transform, (2) circle detection in an image, (3) breaking RSA keys in a network, (4) LZW-compression/decompression (4) Top-k selection, (6) multiple-precision arithmetic.
Experimental results show that our FPGA implementation may be 100 times faster than conventional CPU implementation. This fact implies that FDFM approach is very efficient for general-purpose computing.
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