Epitaxial growth of Ge with low defect density on ultrathin Si layers
| Project/Area Number |
25630121
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | The University of Tokyo |
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Principal Investigator |
Ishikawa Yasuhiko 東京大学, 工学(系)研究科(研究院), 准教授 (60303541)
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| Project Period (FY) |
2013-04-01 – 2016-03-31
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| Project Status |
Completed (Fiscal Year 2015)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2015: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2014: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
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| Keywords | エピタキシャル / 結晶成長 / 電子・電気材料 / 格子欠陥 / 半導体物性 |
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| Outline of Final Research Achievements |
In order to realize epitaxial growth of Ge with a low defect density on SOI (Si-on-Insulator) wafers, Ge epitaxial growth was performed on SOI wafers having ultrathin and patterned top Si layers. A lattice relaxation took place, accompanying a surface roughening and a SiGe alloying, prior to the generation of dislocations in ultrathin Si patterns. Further investigations such as the growth at a reduced temperature are necessary to maintain the layered structures and realize Ge layers with a low dislocation density.
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Report
(4 results)
Research Products
(4 results)
