| Project/Area Number |
25630161
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Communication/Network engineering
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| Research Institution | Osaka University |
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Principal Investigator |
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| Co-Investigator(Kenkyū-buntansha) |
SHIOMI Hidehisa 大阪大学, 大学院基礎工学研究科, 助教 (00324822)
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| Project Period (FY) |
2013-04-01 – 2016-03-31
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| Project Status |
Completed (Fiscal Year 2015)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2015: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2014: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2013: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
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| Keywords | 非線形増幅器 / 周波数利用効率 / 線形化 / アウトフェーズ / 集積回路 / ミリ波サブミリ波通信 / 電力回収 / 電力再利用 / 低歪み高効率増幅 / サブミリ波ベクトル変調波 / シリコン集積回路 / 化合物半導体逓倍器 / 無線通信信号 / 整流回路 / 電力回生 / 線形化電力増幅器 / アウトフェーズ増幅 / 低電圧駆動整流器 |
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| Outline of Final Research Achievements |
Many researchers are now working to reduce power consumption of portable wireless terminals with their high-performance. In digital circuits, the process miniaturization is the major driving force to achieve the low-power consumption. However, we cannot expect to improve the analog circuits by using same method. Conventionally, nonlinear amplifiers with high efficiency are utilized for this purpose. On the other hand, this method is not available for the multilevel modulation for the reason of large signal fluctuation. Here, we propose a newly circuit architecture named out-phase architecture in which a lot of analog circuits are replaced by digital circuits to reduce the power consumption. The proposed architecture can realize many convenient functions such as highly linear power amplifiers, highly linear frequency multipliers and so on. Furthermore, we try to take the power recovery circuits into the proposed circuits to collect the unwanted power and demonstrate their usefulness.
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