| Budget Amount *help |
¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2016: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2015: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2014: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2013: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
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| Outline of Final Research Achievements |
In this research, we developed a novel computer architecture which enables sustainable improvement of the computing performance. By improving the technology in that CPU automatically optimizes the execution at runtime, this study complements the technology that optimizes the execution based on the given instructions by the programmers such as many-core or SIMD technologies. In the first year we proposed an original instruction set which is characterized by eliminating register overwrites, and in the second year we clarified that this feature resolves the weak point of conventional CPUs. In the third year, dedicated compiler is developed, and in the final year our architecture is strengthened by novel HW/SW optimizing technology. These results reveal that the execution efficiency of our architecture is expected to be several times higher than conventional, and this research has shifted to the next stage such as system design and extension to artificial intelligence correspondence.
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