| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2014: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
Fiscal Year 2013: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Outline of Final Research Achievements |
Toward the realization of large-scale on-chip parallel systems, this research project studied the configuration method of dependable Network-on-Chip (NoC) to tolerate defects and faults in the systems. Introducing the concept of partial reconfiguration, we developed a novel approach which combines two different fault-tolerance technologies, network reconfiguration and fault-tolerant routing. This approach has shown to reduce the significant degradation of NoC size and communication performance which was the critical problem in the previous methods, and enable the customization of NoC to meet the performance requirements imposed by the target applications.
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