Configuration Method of Dependable Network-on-Chip Based on Partial Reconfiguration
| Project/Area Number |
25730030
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | Yamaguchi University |
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Principal Investigator |
FUKUSHI MASARU 山口大学, 理工学研究科, 准教授 (50345659)
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| Project Period (FY) |
2013-04-01 – 2015-03-31
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| Project Status |
Completed (Fiscal Year 2014)
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| Budget Amount *help |
¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2014: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
Fiscal Year 2013: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Keywords | ネットワークオンチップ / 高信頼アーキテクチャ / ネットワーク再構成 / 耐故障ルーティング / 部分再構成 |
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| Outline of Final Research Achievements |
Toward the realization of large-scale on-chip parallel systems, this research project studied the configuration method of dependable Network-on-Chip (NoC) to tolerate defects and faults in the systems. Introducing the concept of partial reconfiguration, we developed a novel approach which combines two different fault-tolerance technologies, network reconfiguration and fault-tolerant routing. This approach has shown to reduce the significant degradation of NoC size and communication performance which was the critical problem in the previous methods, and enable the customization of NoC to meet the performance requirements imposed by the target applications.
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Report
(3 results)
Research Products
(17 results)
