Maximize the Efficiency of LSI DesignFlow with Advanced LSI Test Method
| Project/Area Number |
25730031
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | Kyushu Institute of Technology |
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Principal Investigator |
Miyase Kohei 九州工業大学, 大学院情報工学研究院, 助教 (30452824)
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| Project Period (FY) |
2013-04-01 – 2016-03-31
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| Project Status |
Completed (Fiscal Year 2015)
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| Budget Amount *help |
¥3,380,000 (Direct Cost: ¥2,600,000、Indirect Cost: ¥780,000)
Fiscal Year 2015: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2014: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2013: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Keywords | VLSI設計技術 / LSIテスト |
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| Outline of Final Research Achievements |
In this work, we proposed a method to extract important areas in terms of controlling power consuming of LSI testing. Also, we proposed a method to generate test patterns for the extracted areas. The results of above methods can be integrated, and then they can contribute to increase the efficiency of the LSI design flow. The results of extraction of areas can be used for power network synthesis and power-aware test pattern generation. The proposed test pattern generation can contribute to increase effectiveness of detection, reliability, and quality of LSI. We have published this work in two international symposiums, one international workshop, and one Japanese workshop.
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Report
(4 results)
Research Products
(6 results)
