HPC Interconnects toward Ultra-low-delay Era

• Project/Area Number: 25730068
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Multi-year Fund
• Research Field: Information network
• Research Institution: National Institute of Informatics
• Principal Investigator: FUJIWARA Ikki 国立情報学研究所, アーキテクチャ科学研究系, 特任准教授 (90648023)
• Project Period (FY): 2013-04-01 – 2015-03-31
• Project Status: Completed (Fiscal Year 2014)
• Budget Amount: ¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000); Fiscal Year 2014: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000); Fiscal Year 2013: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
• Keywords: ネットワーク / ハイパフォーマンス・コンピューティング / 計算機システム / 相互結合網 / トポロジー

Outline of Final Research Achievements

This research clarified how to design an ultra-low-latency network that connects tens of thousands of computers within a large-scale parallel computing systems such as next-generation supercomputers. We developed a sophisticated method to design a network topology and a routing algorithm that minimizes the end-to-end latency. Existng design method for supercomputer networks did not take a cable delay into account, of which our proposed method explicitly take care. When comparing to a former state-of-the-art network design, our design achieves merely 6% higher communication latency while consuming 65% smaller amount of cable. As such, our proposed design method provides a desirable trade-off between cost and performance.

Research Products

• [Journal Article] Augmenting Low-latency HPC Network with Free-space Optical Links (2015)
  • Author(s): Ikki Fujiwara, Michihiro Koibuchi. Tomoya Ozaki, Hiroki Matsutani, Henri Casanova
  • Journal Title: The 21st IEEE International Symposium on High Performance Computer Architecture (HPCA) Volume: 1 Pages: 390-401
  • DOI: 10.1109/hpca.2015.7056049
  • Peer Reviewed / Open Access / Acknowledgement Compliant
• [Journal Article] Optimized Core-links for Low-latency NoCs (2015)
  • Author(s): Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
  • Journal Title: Proceedings of the 23rd Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP 2015) Volume: - Pages: 172-176
  • DOI: 10.1109/pdp.2015.15
  • Peer Reviewed
• [Journal Article] Swap-and-randomize: A Method for Building Low-latency HPC Interconnects (2014)
  • Author(s): Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova
  • Journal Title: IEEE Transactions on Parallel and Distributed Systems Volume: No.1,PrePrint Issue: 7 Pages: 1-1
  • DOI: 10.1109/tpds.2014.2340863
  • Peer Reviewed / Acknowledgement Compliant
• [Journal Article] Extreme Big Data (EBD): Next Generation Big Data Infrastructure Technologies Towards Yottabyte/Year (2014)
  • Author(s): Satoshi Matsuoka, Hitoshi Sato, Osamu Tatebe, Michihiro Koibuchi, Ikki Fujiwara, Shuji Suzuki, Masanori Kakuta, Takashi Ishida, Yutaka Akiyama, Toyotaro Suzumura, Koji Ueno, Hiroki Kanezashi, Takemasa Miyoshi
  • Journal Title: Supercomputing frontiers and innovations Volume: 1 Pages: 89-107
  • Peer Reviewed / Open Access
• [Journal Article] Layout-aware Expandable Low-degree Topology (2014)
  • Author(s): Nguyen T. Truong, Van K. Nguyen, Nhat T. X. Le, Ikki Fujiwara, Fabian Chaix and Michihiro Koibuchi
  • Journal Title: The 20th IEEE International Conference on Parallel and Distributed Systems (ICPADS) Volume: 1 Pages: 462-470
  • DOI: 10.1109/padsw.2014.7097842
  • Peer Reviewed / Acknowledgement Compliant
• [Journal Article] Skywalk: a Topology for HPC Networks with Low-delay Switches (2014)
  • Author(s): Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova
  • Journal Title: The 28th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2014) Volume: 1
  • Peer Reviewed
• [Journal Article] ランダムなネットワークトポロジのラック配置最適化に関する研究 (2013)
  • Author(s): 藤原一毅, 鯉渕道紘
  • Journal Title: 電子情報通信学会論文誌 Volume: J96-D Pages: 1903-1912
  • Peer Reviewed
• [Journal Article] Mapping Non-trivial Network Topologies onto Chips (2013)
  • Author(s): Ikki Fujiwara, Michihiro Koibuchi
  • Journal Title: The International Symposium on Embedded Multicore/Many-core System-on-Chip (MCSoC-13) Volume: 1 Pages: 73-78
  • DOI: 10.1109/mcsoc.2013.10
  • Peer Reviewed
• [Journal Article] Distributed Shortcut Networks: Layout-Aware Low-Degree Topologies Exploiting Small-World Effect (2013)
  • Author(s): Van K. Nguyen, Nhat T. X. Le, Ikki Fujiwara, Michihiro Koibuchi
  • Journal Title: International Conference of Parallel Processing Volume: 1 Pages: 572-581
  • DOI: 10.1109/icpp.2013.71
  • Peer Reviewed
• [Presentation] Pursuit of Low-latency Networks for Supercomputers (2014)
  • Author(s): 藤原一毅, 鯉渕道紘
  • Organizer: 第10回情報科学ワークショップ
  • Place of Presentation: ツネイシしまなみビレッジ（広島県福山市）
  • Year and Date: 2014-09-17 – 2014-09-19
• [Presentation] 光サーキットの補助による低遅延性及びトポロジ内包性・分割性をもつネットワーク (2014)
  • Author(s): 河野隆太, 藤原一毅, 松谷宏紀, 天野英晴, 鯉渕道紘
  • Organizer: 2014年並列／分散／協調処理に関する『新潟』サマー・ワークショップ (SWoPP新潟2014)
  • Place of Presentation: 朱鷺メッセ（新潟県新潟市）
  • Year and Date: 2014-07-28 – 2014-07-30
• [Presentation] 高次元トポロジNoCの配線長最小化手法 (2013)
  • Author(s): 藤原一毅, 鯉渕道紘
  • Organizer: 2013年並列／分散／協調処理に関する 『北九州』サマー・ワークショップ (SWoPP北九州2013)
  • Place of Presentation: 北九州国際会議場
• [Presentation] Does light speed affect topologies? (2013)
  • Author(s): Ikki Fujiwara
  • Organizer: NII 湘南会議 031 "Many-cores and On-chip Interconnects"
  • Place of Presentation: 湘南国際村センター
• [Remarks] 鯉渕研究室ホームページ
  • URL: http://research.nii.ac.jp/~koibuchi/
• [Remarks] NIIオープンハウス2014
  • URL: http://www.nii.ac.jp/index.php?_restful_permalink=event%2Fopenhouse%2Farchives%2F2014
• [Remarks] 鯉渕研究室ホームページ
  • URL: http://research.nii.ac.jp/~koibuchi/