| Project/Area Number |
26280011
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Partial Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Tohoku University |
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Principal Investigator |
EGAWA RYUSUKE 東北大学, サイバーサイエンスセンター, 准教授 (80374990)
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| Co-Investigator(Kenkyū-buntansha) |
多田 十兵衛 山形大学, 理工学研究科, 助教 (30361273)
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| Co-Investigator(Renkei-kenkyūsha) |
Kobayashi Hiroaki 東北大学, 情報科学研究科, 教授 (40205480)
Takizawa Hiroyuki 東北大学, サイバーサイエンスセンター, 教授 (70323996)
Sato Masayuki 東北大学, 情報科学研究科, 助教 (50781308)
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| Research Collaborator |
Uno Wataru
Nishimura Shin
Hosokawa Mikio
Toyoshima Takuya
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| Project Period (FY) |
2014-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥14,430,000 (Direct Cost: ¥11,100,000、Indirect Cost: ¥3,330,000)
Fiscal Year 2016: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2015: ¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2014: ¥5,070,000 (Direct Cost: ¥3,900,000、Indirect Cost: ¥1,170,000)
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| Keywords | TSV / 低消費電力 / 3次元積層 / 計算機アーキテクチャ / 回路設計 / 三次元積層技術 / 低消費電力アーキテクチャ / 三次元集積技術 / 演算回路 / マイクロアーキテクチャ |
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| Outline of Final Research Achievements |
To clarify the design space of future microprocessors after the end of moor’s law, this research project focuses on vertical integration technologies such as 2.5D and 3D technologies using a through silicon via (TSV). Since the TSVs have a high potential of shortening the latency and reducing the power consumption in/of microprocessors and computing systems, these technologies are expected to overcome the limits of technology scaling. In this research, we explore the design space of the future microprocessors by aggressively using TSVs in various stacking granularities. The evaluation results show that appropriate usage of TSVs with considering a trade-off among performance, power, and cost can drastically improve the energy efficiency of the microprocessors and computer systems.
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